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? 1999 microchip technology inc. advanced information ds41120a-page 1 microcontroller core features: ? high-performance risc cpu ? only 35 single word instructions to learn ? all single cycle instructions except for program branches which are two cycle ? operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle ? interrupt capability (up to 10 internal/external interrupt sources) ? eight level deep hardware stack ? direct, indirect and relative addressing modes ? power-on reset (por) ? power-up timer (pwrt) and oscillator start-up timer (ost) ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? selectable oscillator options: - intrc - internal rc, dual speed (4mhz and 37khz) dynamically switchable for power sav- ings - er - external resistor, dual speed (user selectable frequency and 37khz) dynami- cally switchable for power savings - ec - external clock - hs - high speed crystal/resonator - xt - crystal/resonator - lp - low power crystal ? low-power, high-speed cmos eprom technology ? in-circuit serial programming? (iscp ) ? wide operating voltage range: 2.5v to 5.5v ? 15 i/o pins with individual control for: - direction (15 pins) - digital/analog input (6 pins) - portb interrupt on change (8 pins) - portb weak pull-up (8 pins) - high voltage open drain (1 pin) ? commercial and industrial temperature ranges ? low-power consumption: - < 2 ma @ 5v, 4 mhz - 22.5 m a typical @ 3v, 32 khz -< 1 m a typical standby current pin diagram peripheral features: ? timer0: 8-bit timer/counter with 8-bit prescaler ? timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock ? timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? enhanced capture, compare, pwm (eccp) module - capture is 16 bit, max. resolution is 12.5 ns - compare is 16 bit, max. resolution is 200 ns - pwm max. resolution is 10 bit - enhanced pwm: - single, half-bridge and full-bridge output modes - digitally programmable deadband delay ? analog-to-digital converter: - pic16c770/771 12-bit resolution - pic16c717 10-bit resolution ? on-chip absolute bandgap voltage reference generator ? programmable brown-out reset (pbor) circuitry ? programmable low-voltage detection (plvd) circuitry ? master synchronous serial port (mssp) with two modes of operation: - 3-wire spi? (supports all 4 spi modes) -i 2 c? compatible including master mode support ? program memory read (pmr) capability for look- up table, character string storage and checksum calculation purposes device memory pins a/d resolution a/d channels program x14 data x8 pic16c717 2k 256 18, 20 10 bits 6 pic16c770 2k 256 20 12 bits 6 pic16c771 4k 256 20 12 bits 6 rb3/ccp1/p1a rb2/sck/scl ra7/osc1/clkin ra6/osc2/clkout v dd rb7/t1osi/p1d rb6/t1oso/t1cki/p1c rb5/sdo/p1b rb4/sdi/sda ra0/an0 ra1/an1/lvdin ra4/t0cki ra5/mclr /v pp v ss ra2/an2/v ref -/vrl ra3/an3/v ref +/vrh rb0/an4/int rb1/an5/ss 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 a vdd a vss 10 11 pic16c770/771 20-pin pdip, soic, ssop pic16c717/770/771 18/20-pin, 8-bit cmos microcontrollers with 10/12-bit a/d
pic16c717/770/771 ds41120a-page 2 advanced information ? 1999 microchip technology inc. pin diagrams 18-pin pdip, soic rb3/ccp1/p1a rb2/sck/scl ra7/osc1/clkin ra6/osc2/clkout v dd rb7/t1osi/p1d rb6/t1oso/t1cki/p1c rb5/sdo/p1b rb4/sdi/sda ra0/an0 ra1/an1/lvdin ra4/t0cki ra5/mclr /v pp v ss ra2/an2/v ref -/vrl ra3/an3/v ref +/vrh rb0/an4/int rb1/an5/ss 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 pic16c717 rb3/ccp1/p1a rb2/sck/scl ra7/osc1/clkin ra6/osc2/clkout v dd (2) rb7/t1osi/p1d rb6/t1oso/t1cki/p1c rb5/sdo/p1b rb4/sdi/sda ra0/an0 ra1/an1/lvdin ra4/t0cki ra5/mclr /v pp v ss (1) ra2/an2/v ref -/vrl ra3/an3/v ref +/vrh rb0/an4/int rb1/an5/ss 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 pic16c717 v dd (2) v ss (1) 10 11 20-pin ssop note 1: v ss pins 5 and 6 must be tied together. 2: v dd pins 15 and 16 must be tied together. key features picmicro tm mid-range reference manual (ds33023) pic16c717 pic16c770 pic16c771 operating frequency dc - 20 mhz dc - 20 mhz dc - 20 mhz resets (and delays) por, bor, mclr , wdt (pwrt, ost) por, bor, mclr , wdt (pwrt, ost) por, bor, mclr , wdt (pwrt, ost) program memory (14-bit words) 2k 2k 4k data memory (bytes) 256 256 256 interrupts 10 10 10 i/o ports ports a,b ports a,b ports a,b timers 333 enhanced capture/compare/pwm (eccp) modules 111 serial communications mssp mssp mssp 12-bit analog-to-digital module ? 6 input channels 6 input channels 10-bit analog-to-digital module 6 input channels ?? instruction set 35 instructions 35 instructions 35 instructions
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 3 table of contents 1.0 device overview ............................................................................................................. ...................................... 5 2.0 memory organization......................................................................................................... ................................. 11 3.0 i/o ports................................................................................................................... ........................................... 27 4.0 program memory read (pmr) ................................................................................................... ........................ 43 5.0 timer0 module ............................................................................................................... ..................................... 47 6.0 timer1 module ............................................................................................................... ..................................... 49 7.0 timer2 module ............................................................................................................... ..................................... 53 8.0 enhanced capture/compare/pwm(eccp) modules .................................................................................. ....... 55 9.0 master synchronous serial port (mssp) module................................................................................ ............... 67 10.0 voltage reference module and low-voltage detect............................................................................ ............. 109 11.0 analog-to-digital converter (a/d) module ................................................................................... ..................... 113 12.0 special features of the cpu ................................................................................................ ............................ 125 13.0 instruction set summary.................................................................................................... ............................... 141 14.0 development support ........................................................................................................ ............................... 149 15.0 electrical characteristics................................................................................................. .................................. 155 16.0 dc and ac characteristics graphs and tables ................................................................................ ............... 177 17.0 packaging information ...................................................................................................... ................................ 179 revision history ............................................................................................................. ........................................... 189 device differences ............................................................................................................ ......................................... 189 index ......................................................................................................................... ................................................. 191 on-line support................................................................................................................ .......................................... 197 reader response ................................................................................................................ ....................................... 198 pic16c717/770/771 product identification system ................................................................................ .................... 199 to our valued customers most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number. e.g., ds30000a is version a of document ds30000. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. errata an errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the re vi- sion of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchips worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) ? the microchip corporate literature center; u.s. fax: (480) 786-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de liter- ature number) you are using. corrections to this data sheet we constantly strive to improve the quality of all our products and documentation. we have spent a great deal of time to ensure that this document is correct. however, we realize that we may have missed a few things. if you find any information that is mi ssing or appears in error, please: ? fill out and mail in the reader response form in the back of this data sheet. ? e-mail us at webmaster@microchip.com. we appreciate your assistance in making this a better document.
pic16c717/770/771 ds41120a-page 4 advanced information ? 1999 microchip technology inc. notes:
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 5 1.0 device overview this document contains device-specific information. additional information may be found in the picmicro tm mid-range reference manual, (ds33023), which may be obtained from your local microchip sales represen- tative or downloaded from the microchip website. the reference manual should be considered a comple- mentary document to this data sheet, and is highly rec- ommended reading for a better understanding of the device architecture and operation of the peripheral modules. there are three devices (pic16c717, pic16c770 and pic16c771) covered by this datasheet. the pic16c717 device comes in 18/20-pin packages and the pic16c770/771 devices come in 20-pin packages. the following two figures are device block diagrams of the pic16c717 and the pic16c770/771. figure 1-1: pic16c717 block diagram eprom program memory 2k x 14 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 256 x 8 direct addr 7 addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control osc1/clkin osc2/clkout v dd , v ss porta portb ra4/t0cki rb0/an4/int rb4/sdi/sda 8 8 brown-out reset note 1: higher order bits are from the status register. enhanced ccp master timer0 timer1 timer2 synchronous ra3/an3/v ref +/vrh ra2/an2/v ref -/vrl ra1/an1/lvdin ra0/an0 8 3 timing generation 10-bit adc rb1/an5/ss rb2/sck/scl rb3/ccp1/p1a ra5/mclr /v pp ra6/osc2/clkout ra7/osc1/clkin rb5/sdo/p1b rb6/t1oso/t1cki/p1c rb7/t1osi/p1o internal 4mhz, 37khz and er mode (eccp1) serial port (mssp) bandgap reference low-voltage detect ram program memory read (pmr)
pic16c717/770/771 ds41120a-page 6 advanced information ? 1999 microchip technology inc. figure 1-2: pic16c770/771 block diagram eprom program memory (2) 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 256 x 8 direct addr 7 addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control osc1/clkin osc2/clkout v dd , v ss porta portb ra4/t0cki rb0/an4/int rb4/sdi/sda 8 8 brown-out reset note 1: higher order bits are from the status register. 2: program memory for pic16c770 is 2k x 14. program memory for pic16c771 is 4k x 14. enhanced ccp master timer0 timer1 timer2 synchronous ra3/an3/v ref +/vrh ra2/an2/v ref -/vrl ra1/an1/lvdin ra0/an0 8 3 timing generation 12-bit adc rb1/an5/ss rb2/sck/scl rb3/ccp1/p1a ra5/mclr /v pp ra6/osc2/clkout ra7/osc1/clkin rb5/sdo/p1b rb6/t1oso/t1cki/p1c rb7/t1osi/p1o internal 4mhz, 37khz and er mode (eccp1) serial port (mssp) bandgap reference low-voltage detect ram program memory read (pmr) av dd av ss
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 7 table 1-1: pic16c770/771 pinout description name function input type output type description ra0/an0 ra0 st cmos bi-directional i/o an0 an a/d input ra1/an1/lvdin ra1 st cmos bi-directional i/o an1 an a/d input lvdin an lvd input reference ra2/an2/v ref -/vrl ra2 st cmos bi-directional i/o an2 an a/d input v ref - an negative analog reference input vrl an internal voltage reference low output ra3/an3/v ref +/vrh ra3 st cmos bi-directional i/o an3 an a/d input v ref + an positive analog reference input vrh an internal voltage reference high output ra4/t0cki ra4 st od bi-directional i/o t0cki st tmr0 clock input ra5/mclr /v pp ra5 st input port mclr st master clear v pp power programming voltage ra6/osc2/clkout ra6 st cmos bi-directional i/o osc2 xtal crystal/resonator clkout cmos f osc /4 output ra7/osc1/clkin ra7 st cmos bi-directional i/o osc1 xtal crystal/resonator clkin st external clock input/er resistor connection rb0/an4/int rb0 ttl cmos bi-directional i/o (1) an4 an a/d input int st interrupt input rb1/an5/ss rb1 ttl cmos bi-directional i/o (1) an5 an a/d input ss st ssp slave select input rb2/sck/scl rb2 ttl cmos bi-directional input (1) sck st cmos serial clock i/o for spi scl st od serial clock i/o for i 2 c rb3/ccp1/p1a rb3 ttl cmos bi-directional input (1) ccp1 st cmos capture 1 input/compare 1 output p1a cmos pwm p1a output rb4/sdi/sda rb4 ttl cmos bi-directional input (1) sdi st serial data in for spi sda st od serial data i/o for i 2 c rb5/sdo/p1b rb5 st cmos bi-directional i/o (1) sdo cmos serial data out for spi p1b cmos pwm p1b output note 1: bit programmable pull-ups.
pic16c717/770/771 ds41120a-page 8 advanced information ? 1999 microchip technology inc. rb6/t1oso/t1cki/p1c rb6 ttl cmos bi-directional i/o (1) t1oso xtal crystal/resonator t1cki st tmr1 clock input p1c cmos pwm p1c output rb7/t1osi/p1d rb7 ttl cmos bi-directional i/o (1) t1osi xtal tmr1 crystal/resonator p1d cmos pwm p1d output v ss v ss power ground reference for logic and i/o pins v dd v dd power positive supply for logic and i/o pins av ss av ss power ground reference for analog av dd av dd power positive supply for analog table 1-1: pic16c770/771 pinout description (continued) name function input type output type description note 1: bit programmable pull-ups.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 9 table 1-2: pic16c717 pinout description name function input type output type description ra0/an0 ra0 st cmos bi-directional i/o an0 an a/d input ra1/an1/lvdin ra1 st cmos bi-directional i/o an1 an a/d input reference lvdin an lvd input reference ra2/an2/v ref -/vrl ra2 st cmos bi-directional i/o an2 an a/d input v ref - an negative analog reference input vrl an internal voltage reference low output ra3/an3/v ref +/vrh ra3 st cmos bi-directional i/o an3 an a/d input v ref + an positive analog reference high output vrh an internal voltage reference high output ra4/t0cki ra4 st od bi-directional i/o t0cki st tmr0 clock input ra5/mclr /v pp ra5 st input port mclr st master clear v pp power programming voltage ra6/osc2/clkout ra6 st cmos bi-directional i/o osc2 xtal crystal/resonator clkout cmos f osc /4 output ra7/osc1/clkin ra7 st cmos bi-directional i/o osc1 xtal crystal/resonator clkin st external clock input/er resistor connection rb0/an4/int rb0 ttl cmos bi-directional i/o (1) an4 an a/d input int st interrupt input rb1/an5/ss rb1 ttl cmos bi-directional i/o (1) an5 an a/d input ss st ssp slave select input rb2/sck/scl rb2 ttl cmos bi-directional input (1) sck st cmos serial clock i/o for spi scl st od serial clock i/o for i 2 c rb3/ccp1/p1a rb3 ttl cmos bi-directional input (1) ccp1 st cmos capture 1 input/compare 1 output p1a cmos pwm p1a output rb4/sdi/sda rb4 ttl cmos bi-directional input (1) sdi st serial data in for spi sda st od serial data i/o for i 2 c rb5/sdo/p1b rb5 st cmos bi-directional i/o (1) sdo cmos serial data out for spi p1b cmos pwm p1b output note 1: bit programmable pull-ups.
pic16c717/770/771 ds41120a-page 10 advanced information ? 1999 microchip technology inc. rb6/t1oso/t1cki/p1c rb6 ttl cmos bi-directional i/o (1) t1oso xtal tmr1 crystal/resonator t1cki st tmr1 clock input p1c cmos pwm p1c output rb7/t1osi/p1d rb7 ttl cmos bi-directional i/o (1) t1osi xtal tmr1 crystal/resonator p1d cmos pwm p1d output v ss v ss power ground v dd v dd power positive supply table 1-2: pic16c717 pinout description (continued) name function input type output type description note 1: bit programmable pull-ups.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 11 2.0 memory organization there are two memory blocks in each of these picmicro ? microcontrollers. each block (pro- gram memory and data memory) has its own bus, so that concurrent access can occur. additional information on device memory may be found in the picmicro ? mid-range reference manual, (ds33023). 2.1 program memory organization the pic16c717/770/771 devices have a 13-bit pro- gram counter capable of addressing an 8k x 14 pro- gram memory space. the pic16c717 and the pic16c770 have 2k x 14 words of program memory. the pic16c771 has 4k x 14 words of program mem- ory. accessing a location above the physically imple- mented address will cause a wraparound. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 2-1: program memory map and stack of the pic16c717 and pic16c770 figure 2-2: program memory map and stack of the pic16c771 2.2 data memory organization the data memory is partitioned into multiple banks, which contain the general purpose registers and the special function registers. bits rp1 and rp0 are the bank select bits. = 00 ? bank0 = 01 ? bank1 = 10 ? bank2 = 11 ? bank3 each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are general purpose registers, implemented as static ram. all implemented banks contain special function registers. some frequently used special func- tion registers from one bank are mirrored in another bank for code reduction and quicker access. 2.2.1 general purpose register file the register file can be accessed either directly, or indi- rectly, through the file select register fsr. pc<12:0> 13 0000h 0004h 0005h stack level 1 stack level 8 reset vector interrupt vector on-chip call, return retfie, retlw stack level 2 program memory page 0 07ffh 3fffh rp1 rp0 (status<6:5>) pc<12:0> 13 0000h 0004h 0005h stack level 1 stack level 8 reset vector interrupt vector on-chip call, return retfie, retlw stack level 2 program memory page 0 page 1 07ffh 0800h 0fffh 1000h 3fffh
pic16c717/770/771 ds41120a-page 12 advanced information ? 1999 microchip technology inc. figure 2-3: register file map indirect addr. (*) tmr0 pcl status fsr porta portb pclath intcon pir1 tmr1l tmr1h t1con tmr2 t2con sspbuf sspcon ccpr1l ccpr1h ccp1con option_reg pcl status fsr trisa trisb pclath intcon pie1 pcon pr2 sspadd sspstat 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 unimplemented data memory locations, read as '0'. * not a physical register. indirect addr. (*) adresl pir2 pie2 adresh adcon0 adcon1 general purpose register general purpose register efh f0h accesses 70h-7fh 96 bytes 80 bytes lvdcon 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 10ch 10dh 10eh 10fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11ah 11bh 11ch 11dh 11eh 11fh 120h 17fh bank 2 6fh 70h file address pcl status fsr pclath intcon 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh 18ch 18dh 18eh 18fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19ah 19bh 19ch 19dh 19eh 19fh 1a0h 1ffh bank 3 indirect addr. (*) option_reg 1efh 1f0h accesses 70h - 7fh trisb pcl status fsr pclath intcon indirect addr. (*) tmr0 general purpose register accesses 70h - 7fh portb 80 bytes file address file address file address refcon sspcon2 wpub iocb ansel p1del pmdatl pmadrl pmdath pmadrh pmcon1
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 13 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is given in ta bl e 2 - 1 . the special function registers can be classified into two sets; core (cpu) and peripheral. those registers asso- ciated with the core functions are described in detail in this section. those related to the operation of the peripheral features are described in detail in that peripheral feature section. table 2-1: pic16c717/770/771 special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) bank 0 00h (3) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h (3) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 03h (3) status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 04h (3) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx 0000 uuuu 0000 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xx00 uuuu uu00 07h unimplemented 08h unimplemented 09h unimplemented 0ah (1,3) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh (3) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 0dh pir2 lvdif bclif 0--- 0--- 0--- 0--- 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con pwm1m1 pwm1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 18h unimplemented 19h unimplemented 1ah unimplemented 1bh unimplemented 1ch unimplemented 1dh unimplemented 1eh adresh a/d high byte result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done chs3 adon 0000 0000 0000 0000 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as 0. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose con- tents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: these registers can be addressed from any bank.
pic16c717/770/771 ds41120a-page 14 advanced information ? 1999 microchip technology inc. bank 1 80h (3) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (3) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 83h (3) status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 84h (3) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa porta data direction register 1111 1111 1111 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h unimplemented 88h unimplemented 89h unimplemented 8ah (1,3) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh (3) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 8dh pie2 lvdie bclie 0--- 0--- 0--- 0--- 8eh pcon oscf por bo r ---- 1-qq ---- 1-uu 8fh unimplemented 90h unimplemented 91h sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 94h sspstat smp cke d/a psr/w ua bf 0000 0000 0000 0000 95h wpub portb weak pull-up control 1111 1111 1111 1111 96h iocb portb interrupt on change control 1111 0000 1111 0000 97h p1del pwm 1 delay value 0000 0000 0000 0000 98h unimplemented 99h unimplemented 9ah unimplemented 9bh refcon vrhen vrlen vrhoen vrloen 0000 ---- 0000 ---- 9ch lvdcon bgst lvden lvv3 lvv2 lvv1 lvv0 --00 0101 --00 0101 9dh ansel analog channel select 1111 1111 1111 1111 9eh adresl a/d low byte result register xxxx xxxx uuuu uuuu 9fh adcon1 adfm vcfg2 vcfg1 vcfg0 0000 0000 0000 0000 table 2-1: pic16c717/770/771 special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as 0. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose con- tents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: these registers can be addressed from any bank.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 15 bank 2 100h (3) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 101h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 102h (3) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 103h (3) status irp rp1 rp0 to pd z dc c 0001 1xxx 000q quuu 104h (3) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 105h unimplemented 106h portb portb data latch when written: portb pins when read xxxx xx00 uuuu uu00 107h unimplemented 108h unimplemented 109h unimplemented 10ah (1,3) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 10bh (3) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 10ch pmdatl program memory read data low xxxx xxxx uuuu uuuu 10dh pmadrl program memory read address low xxxx xxxx uuuu uuuu 10eh pmdath program memory read data high --xx xxxx --uu uuuu 10fh pmadrh program memory read address high ---- xxxx ---- uuuu 110h- 11fh unimplemented bank 3 180h (3) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 182h (3) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 183h (3) status irp rp1 rp0 to pd z dc c 0001 1xxx 000q quuu 184h (3) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 185h unimplemented 186h trisb portb data direction register 1111 1111 1111 1111 187h unimplemented 188h unimplemented 189h unimplemented 18ah (1,3) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 18bh (3) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 18ch pmcon1 reserved rd 1--- ---0 1--- ---0 18dh- 18fh unimplemented table 2-1: pic16c717/770/771 special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as 0. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose con- tents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: these registers can be addressed from any bank.
pic16c717/770/771 ds41120a-page 16 advanced information ? 1999 microchip technology inc. 2.2.2.1 status register the status register, shown in register 2-1 , contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect the z, c or dc bits from the status register. for other instructions not affecting any status bits, see the "instruction set summary." register 2-1: status register (status: 03h, 83h, 103h, 183h) note 2: the c and dc bits operate as a borrow and digit borrow bit, respectively, in subtraction. see the sublw and subwf instructions for examples. r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd z dc c r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: irp: register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) bit 6-5: rp<1:0>: register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes bit 4: to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc: digit carry/borrow bit ( addwf , addlw,sublw,subwf instructions) (for borrow the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0: c: carry/borrow bit ( addwf , addlw,sublw,subwf instructions) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow , the polarity is reversed. a subtraction is executed by adding the twos complement of the sec- ond operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high or low order bit of the source register.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 17 2.2.2.2 option_reg register the option_reg register is a readable and writable register, which contains various control bits to configure the tmr0 prescaler/wdt postscaler (single assign- able register known also as the prescaler), the external int interrupt, tmr0 and the weak pull-ups on portb. register 2-2: option register (option_reg: 81h, 181h) note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: rbpu : portb pull-up enable bit (1) 1 = portb weak pull-ups are disabled 0 = portb weak pull-ups are enabled by the wpub register bit 6: intedg: interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5: t0cs: tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se: tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3: psa: prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0: ps<2:0>: prescaler rate select bits note 1: individual weak pull-up on rb pins can be enabled/disabled from the weak pull-up portb register (wpub). 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
pic16c717/770/771 ds41120a-page 18 advanced information ? 1999 microchip technology inc. 2.2.2.3 intcon register the intcon register is a readable and writable regis- ter, which contains various enable and flag bits for the tmr0 register overflow, rb port change and external rb0/int pin interrupts. register 2-3: interrupt control register (intcon: 0bh, 8bh, 10bh, 18bh) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte rbie t0if intf rbif r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: gie: global interrupt enable bit 1 = enables all un-masked interrupts 0 = disables all interrupts bit 6: peie: peripheral interrupt enable bit 1 = enables all un-masked peripheral interrupts 0 = disables all peripheral interrupts bit 5: t0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4: inte: rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3: rbie: rb port change interrupt enable bit (1) 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2: t0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1: intf: rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0: rbif: rb port change interrupt flag bit (1) 1 = at least one of the rb<7:0> pins changed state (must be cleared in software) 0 = none of the rb<7:0> pins have changed state note 1: individual rb pin interrupt on change can be enabled/disabled from the interrupt on change portb register (iocb).
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 19 2.2.2.4 pie1 register this register contains the individual enable bits for the peripheral interrupts. register 2-4: peripheral interrupt enable register 1 (pie1: 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adie sspie ccp1ie tmr2ie tmr1ie r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: unimplemented: read as 0 bit 6: adie: a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5-4: unimplemented: read as 0 bit 3: sspie: synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2: ccp1ie: ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1: tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0: tmr1ie: tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt
pic16c717/770/771 ds41120a-page 20 advanced information ? 1999 microchip technology inc. 2.2.2.5 pir1 register this register contains the individual flag bits for the peripheral interrupts. register 2-5: peripheral interrupt register 1 (pir1: 0ch) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adif sspif ccp1if tmr2if tmr1if r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: unimplemented: r ead as 0. bit 6: adif: a/d converter interrupt flag bit 1 = an a/d conversion completed 0 = the a/d conversion is not complete bit 5-4: unimplemented: read as 0. bit 3: sspif: synchronous serial port (ssp) interrupt flag 1 = the ssp interrupt condition has occurred, and must be cleared in software before returning from the interrupt service routine. the conditions that will set this bit are: spi a transmission/reception has taken place. i 2 c slave / master a transmission/reception has taken place. i 2 c master the initiated start condition was completed by the ssp module. the initiated stop condition was completed by the ssp module. the initiated restart condition was completed by the ssp module. the initiated acknowledge condition was completed by the ssp module. a start condition occurred while the ssp module was idle (multimaster system). a stop condition occurred while the ssp module was idle (multimaster system). 0 = no ssp interrupt condition has occurred. bit 2: ccp1if: ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred c ompare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred p wm mode unused in this mode bit 1: tmr2if: tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0: tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 21 2.2.2.6 pie2 register this register contains the individual enable bits for the ssp bus collision and low voltage detect interrupts. register 2-6: peripheral interrupt register 2 (pie2: 8dh) r/w-0 u-0 u-0 u-0 r/w-0 u-0 u-0 u-0 lv d ie bclie r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: lv d i e : low-voltage detect interrupt enable bit 1 = lvd interrupt is enabled 0 = lvd interrupt is disabled bit 6-4: unimplemented: read as '0' bit 3: bclie: bus collision interrupt enable bit 1 = bus collision interrupt is enabled 0 = bus collision interrupt is disabled bit 2-0: unimplemented: read as '0'
pic16c717/770/771 ds41120a-page 22 advanced information ? 1999 microchip technology inc. 2.2.2.7 pir2 register this register contains the ssp bus collision and low- voltage detect interrupt flag bits. . register 2-7: peripheral interrupt register 2 (pir2: 0dh) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. r/w-0 u-0 u-0 u-0 r/w-0 u-0 u-0 u-0 lv d i f bclif r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: lv d i f : low-voltage detect interrupt flag bit 1 = the supply voltage has fallen below the specified lvd voltage (must be cleared in software) 0 = the supply voltage is greater than the specified lvd voltage bit 6-4: unimplemented: read as '0' bit 3: bclif: bus collision interrupt flag bit 1 = a bus collision has occurred while the ssp module configured in i 2 c master was transmitting (must be cleared in software) 0 = no bus collision occurred bit 2-0: unimplemented: read as '0'
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 23 2.2.2.8 pcon register the power control (pcon) register contains a flag bit to allow differentiation between a power-on reset (por) to an external mclr reset or wdt reset. those devices with brown-out detection circuitry con- tain an additional bit to differentiate a brown-out reset condition from a power-on reset condition. the pcon register also contains the frequency select bit of the intrc or er oscillator. register 2-8: power control register (pcon: 8eh) note: bo r is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bo r is clear, indicating a brown-out has occurred. the bo r status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the boden bit in the configuration word). u-0 u-0 u-0 u-0 r/w-1 u-0 r/w-q r/w-q oscf por bo r r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-4,2: unimplemented: read as '0' bit 3: oscf: oscillator speed intrc mode 1 = 4 mhz nominal 0 = 37 khz nominal er mode 1 = oscillator frequency depends on the external resistor value on the osc1 pin. 0 = 37 khz nominal all other modes x = ignored bit 1: por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0: bo r : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs)
pic16c717/770/771 ds41120a-page 24 advanced information ? 1999 microchip technology inc. 2.3 pcl and pclath the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 13 bits wide. the low byte is called the pcl register. this reg- ister is readable and writable. the high byte is called the pch register. this register contains the pc<12:8> bits and is not directly readable or writable. all updates to the pch register occur through the pclath register. 2.3.1 program memory paging pic16c717/770/771 devices are capable of address- ing a continuous 8k word block of program memory. the call and goto instructions provide only 11 bits of address to allow branching within any 2k program memory page. when doing a call or goto instruction, the upper 2 bits of the address are provided by pclath<4:3>. when doing a call or goto instruc- tion, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. a return instruction pops a pc address off the stack onto the pc register. therefore, manipulation of the pclath<4:3> bits are not required for the return instructions (which pops the address from the stack). 2.4 stack the stack allows a combination of up to 8 program calls and interrupts to occur. the stack contains the return address from this branch in program execution. mid-range devices have an 8-level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execution. pclath is not modified when the stack is pushed or poped. after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on).
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 25 the indf register is not a physical register. address- ing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. reading indf itself indirectly (fsr = 0) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 2-1 . example 2-1: how to clear ram using indirect addressing movlw 0x20 ;initialize pointer movwf fsr ; to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 2-4 . figure 2-4: direct/indirect addressing note 1: for register file map detail see figure 2-3 . data memory (1) indirect addressing direct addressing bank select location select rp1:rp0 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 ffh 80h 7fh 00h 17fh 100h 1ffh 180h
pic16c717/770/771 ds41120a-page 26 advanced information ? 1999 microchip technology inc. notes:
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 27 3.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. additional information on i/o ports may be found in the picmicro? mid-range reference manual, (ds33023). 3.1 i/o port analog/digital mode the pic16c717/770/771 have two i/o ports: porta and portb. some of these port pins are mixed-signal (can be digital or analog). when an analog signal is present on a pin, the pin must be configured as an ana- log input to prevent unnecessary current draw from the power supply. the analog select register (ansel) allows the user to individually select the digital/analog mode on these pins. when the analog mode is active, the port pin will always read 0. register 3-1: analog select register (ansel: 9dh) 3.2 porta and the trisa register porta is a 8-bit wide bi-directional port. the corre- sponding data direction register is trisa. setting a trisa bit (=1) will make the corresponding porta pin an input, i.e., put the corresponding output driver in a hi-impedance mode. clearing a trisa bit (=0) will make the corresponding porta pin an output, i.e., put the contents of the output latch on the selected pin. reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. pins ra<3:0> are multiplexed with analog functions, such as analog inputs to the a/d converter, analog vref inputs, and the on-board bandgap reference out- puts. when the analog peripherals are using any of these pins as analog input/output, the ansel register must have the proper value to individually select the analog mode of the corresponding pins. pin ra4 is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/t0cki pin is a schmitt trigger input and an open drain output. pin ra5 is multiplexed with the device reset (mclr ) and programming input (v pp ) functions. the ra5/ mclr /v pp input only pin has a schmitt trigger input buffer. all other ra port pins have schmitt trigger input buffers and full cmos output buffers. pins ra6 and ra7 are multiplexed with the oscillator input and output functions. the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. note 1: on a power-on reset, the ansel register configures these mixed-signal pins as analog mode. 2: if a pin is configured as analog mode, the pin will always read '0', even if the digital output is active. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ans5 ans4 ans3 ans2 ans1 ans0 r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por reset bit7 bit0 bit 7-6: reserved: do not use bit 5-0: ans<5:0>: analog select between analog or digital function on pins an<5:0>, respectively. 0 = digital i/o. pin is assigned to port or special function. 1 = analog input. pin is assigned as analog input. note: setting a pin to an analog input disables digital inputs and any pull-up that may be present. the corre- sponding tris bit should be set to input mode when using pins as analog inputs. note: upon reset, the ansel register configures the ra<3:0> pins as analog inputs. all ra<3:0> pins will read as '0'.
pic16c717/770/771 ds41120a-page 28 advanced information ? 1999 microchip technology inc. example 3-1: initializing porta bcf status, rp0 ; select bank 0 clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0fh ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<7:4> as outputs. ra<7:6>availability depends on oscillator selection. movlw 03 ; set ra<1:0> as analog inputs, ra<7:2> are digital i/o movwf ansel bcf status, rp0 ; return to bank 0 figure 3-1: block diagram of ra0/an0, ra1/an1/lvdin data bus q d q ck q d q ck qd en p n wr port wr tris data latch tris mode v ss v dd schmitt tr i g g e r to a/d converter input or lvd module input rd tris q d q ck analog select wr ansel rd port v dd v ss
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 29 figure 3-2: block diagram of ra2/an2/v ref -/vrl and ra3/an3/v ref +/vrh to a/d converter input vrh, vrl outputs (from vref-lvd-bor module) and vref+, vref- inputs sense input for vrh, vrl amplifier vrh, vrl output enable data bus q d q ck q d q ck p n wr port wr tris data latch tris mode v ss v dd schmitt trigger rd tris q d q ck analog select wr ansel rd port v dd v ss qd en
pic16c717/770/771 ds41120a-page 30 advanced information ? 1999 microchip technology inc. figure 3-3: block diagram of ra4/t0cki data bus q d q ck q d q ck qd en n wr port wr tris data latch rd v ss schmitt trigger input buffer tmr0 clock input rd tris tris latch port v ss
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 31 figure 3-4: block diagram of ra5/mclr /v pp data bus qd en rd port schmitt trigger rd tris v ss to m c l r circuit mclr filter v ss hv detect program mode
pic16c717/770/771 ds41120a-page 32 advanced information ? 1999 microchip technology inc. figure 3-5: block diagram of ra6/osc2/clkout pin data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta v ss v dd q d q ck schmitt trigger input buffer oscillator circuit from osc1 1 0 clkout (f osc /4) intrc or er with clkout v dd v ss d q en intrc or er without clkout intrc or er with clkout intrc or er
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 33 figure 3-6: block diagram of ra7/osc1/clkin pin data bus q d q ck p n wr porta wr trisa data latch tris latch rd trisa rd porta v ss v dd q d q ck schmitt trigger input buffer oscillator circuit to osc2 intrc intrc schmitt trigger input buffer to chip clock drivers ec mode v dd d q en
pic16c717/770/771 ds41120a-page 34 advanced information ? 1999 microchip technology inc. table 3-1: porta functions name function input type output type description ra0/an0 ra0 st cmos bi-directional i/o an0 an a/d input ra1/an1/lvdin ra1 st cmos bi-directional i/o an1 an a/d input lvdin an lvd input reference ra2/an2/v ref -/vrl ra2 st cmos bi-directional i/o an2 an a/d input v ref - an negative analog reference input vrl an internal voltage reference low output ra3/an3/v ref +/vrh ra3 st cmos bi-directional i/o an3 an a/d input v ref + an positive analog reference input vrh an internal voltage reference high output ra4/t0cki ra4 st od bi-directional i/o t0cki st tmr0 clock input ra5/mclr /v pp ra5 st input port mclr st master clear v pp power programming voltage ra6/osc2/clkout ra6 st cmos bi-directional i/o osc2 xtal crystal/resonator clkout cmos f osc /4 output ra7/osc1/clkin ra7 st cmos bi-directional i/o osc1 xtal crystal/resonator clkin st external clock input/er resistor connection
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 35 table 3-2: summary of registers associated with porta 3.3 p ortb and the trisb register portb is an 8-bit wide bi-directional port. the corre- sponding data direction register is trisb. setting a trisb bit (=1) will make the corresponding portb pin an input, i.e., put the corresponding output driver in a hi-impedance mode. clearing a trisb bit (=0) will make the corresponding portb pin an output, i.e., put the contents of the output latch on the selected pin. example 3-2: initializing portb bcf status, rp0 ; clrf portb ; initialize portb by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs movlw 03 ; set rb<1:0> as analog inputs movwf ansel ; bcf status, rp0 ; return to bank 0 each of the portb pins has an internal pull-up, which can be individually enabled from the wpub register. a single global enable bit can turn on/off the enabled pull- ups. clearing the r bpu bit, (option_reg<7>), enables the weak pull-up resistors. the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. each of the portb pins, if configured as input, also has an interrupt on change feature, which can be indi- vidually selected from the iocb register. the rbie bit in the intcon register functions as a global enable bit to turn on/off the interrupt on change feature. the selected inputs are compared to the old value latched on the last read of portb. the "mismatch" outputs are or'ed together to generate the rb port change inter- rupt with flag bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the inter- rupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt on change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt on change feature. polling of portb is not recommended while using the interrupt on change feature. register 3-2: weak pull up portb register (wpub: 95h) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 05h porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx 0000 uuuu 0000 85h trisa porta data direction register 1111 1111 1111 1111 9dh ansel ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by porta. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por reset bit7 bit0 bit 7-0: wpub<7:0>: portb weak pull-up control 1 = weak pull up enabled. 0 = weak pull up disabled note 1: for the wpub register setting to take effect, the rbpu bit in the option_reg register must be cleared. 2: the weak pull up device is automatically disabled if the pin is in output mode (tris = 0).
pic16c717/770/771 ds41120a-page 36 advanced information ? 1999 microchip technology inc. register 3-3: interrupt on change portb register (iocb: 96h) r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 iocb7 iocb6 iocb5 iocb4 iocb3 iocb2 iocb1 iocb0 r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por reset bit7 bit0 bit 7-0: iocb<7:0>: interrupt on change portb control 1 = interrupt on change enabled. 0 = interrupt on change disabled. note 1: the interrupt enable bits gie and rbie in the intcon register must be set for individual interrupts to be recognized.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 37 the rb0 pin is multiplexed with the a/d converter ana- log input 4 and the external interrupt input (rb0/an4/ int). when the pin is used as analog input, the ansel register must have the proper value to select the rb0 pin as analog mode. the rb1 pin is multiplexed with the a/d converter ana- log input 5 and the mssp module slave select input (rb1/an5/ss). when the pin is used as analog input, the ansel register must have the proper value to select the rb1 pin as analog mode. figure 3-7: block diagram of rb0/an4/int, rb1/an5/ss pin note: upon reset, the ansel register configures the rb1 and rb0 pins as analog inputs. both rb1 and rb0 pins will read as '0'. data bus wr wr rd portb reg tris reg to int input or mssp module q d ck q d ck en qd en rd rbpu weak pull-up ttl schmitt trigger p n v ss v dd q d ck q d ck wpub reg iocb reg port tris port tris wr wpub q d q en d q en q3 q1 ... set rbif from rb<7:0> pins q q d q ck analog select wr ansel wr iocb v dd v ss q p v dd q to a/d converter
pic16c717/770/771 ds41120a-page 38 advanced information ? 1999 microchip technology inc. figure 3-8: block diagram of rb2/sck/scl, rb3/ccp1/p1a, rb4/sdi/sda, rb5/sdo/p1b data bus wr wr rd portb reg tris reg sck, scl, cc, sdi, sda inputs q d ck q d ck en qd en rd rbpu weak pull-up schmitt trigger p n v ss v dd q d ck q d ck wpub reg iocb reg port tris port tris wr wpub q d q en d q en q3 q1 ... set rbif from rb<7:0> pins q wr iocb v dd v ss q p v dd q 1 0 spec. func en. sda, sdo, sck, ccpl, p1a, p1b ttl
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 39 figure 3-9: block diagram of rb6/t1oso/t1cki/p1c data latch tris latch rd trisb p v ss q d q ck q d q ck n v dd rd portb wr portb wr trisb schmitt tr i g g e r t1oscen tmr1 clock rbpu v dd weak pull-up p from rb7 from qd en set rbif rb<7:0> pins rd port q3 q1 serial programming clock ttl input buffer tmr1 oscillator qd en v dd data bus q d ck wpub reg wr wpub q iocb reg wr iocb q d ck q note: the tmr1 oscillator enable (t1oscen = 1) overrides the rb6 i/o port and p1c functions. ...
pic16c717/770/771 ds41120a-page 40 advanced information ? 1999 microchip technology inc. figure 3-10: block diagram of the rb7/t1osi/p1d data latch tris latch rd trisb p v ss q d q ck q d q ck n v dd rd portb wr portb wr trisb t10scen t1oscen to r b 6 rbpu v dd weak pull-up p ttl input buffer from qd en qd en set rbif rb<7:0> pins rd port q3 q1 serial programming input schmitt trigger tmr1 oscillator v dd data bus q d ck wpub reg wr wpub q q d ck iocb reg wr iocb q note: the tmr1 oscillator enable (t1oscen = 1) overrides the rb7 i/o port and p1d functions. ...
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 41 table 3-3: portb functions table 3-4: summary of registers associated with portb name function input type output type description rb0/an4/int rb0 ttl cmos bi-directional i/o (1) an4 an a/d input int st interrupt input rb1/an5/ss rb1 ttl cmos bi-directional i/o (1) an5 an a/d input ss st ssp slave select input rb2/sck/scl rb2 ttl cmos bi-directional input (1) sck st cmos serial clock i/o for spi scl st od serial clock i/o for i 2 c rb3/ccp1/p1a rb3 ttl cmos bi-directional input (1) ccp1 st cmos capture 1 input/compare 1 output p1a cmos pwm p1a output rb4/sdi/sda rb4 ttl cmos bi-directional input (1) sdi st serial data in for spi sda st od serial data i/o for i 2 c rb5/sdo/p1b rb5 st cmos bi-directional i/o (1) sdo cmos serial data out for spi p1b cmos pwm p1b output rb6/t1oso/t1cki/p1c rb6 ttl cmos bi-directional i/o (1) t1oso xtal crystal/resonator t1cki st tmr1 clock input p1c cmos pwm p1c output rb7/t1osi/p1d rb7 ttl cmos bi-directional i/o (1) t1osi xtal tmr1 crystal/resonator p1d cmos pwm p1d output note 1: bit programmable pull-ups. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 06h, 106h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xx00 uuuu uu00 86h, 186h trisb portb data direction register 1111 1111 1111 1111 81h, 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 95h wpub portb weak pull-up control 1111 1111 1111 1111 96h iocb portb interrupt on change control 1111 0000 1111 0000 9dh ansel ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
pic16c717/770/771 ds41120a-page 42 advanced information ? 1999 microchip technology inc. notes:
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 43 4.0 program memory read (pmr) program memory is readable during normal operation (full v dd range). it is indirectly addressed through the special function registers: ?pmcon1 ?pmdath ?pmdatl ? pmadrh ? pmadrl when interfacing the program memory block, the pmdath & pmdatl registers form a 2-byte word, which holds the 14-bit data. the pmadrh & pmadrl registers form a 2-byte word, which holds the 12-bit address of the program memory location being accessed. mid-range devices have up to 8k words of program eprom with an address range from 0h to 3fffh. when the device contains less memory than the full address range of the pmadrh:pmardl regis- ters, the most significant bits of the pmadrh register are ignored. 4.0.1 pmcon1 register pmcon1 is the control register for program memory accesses. control bit rd initiates a read operation. this bit cannot be cleared, only set, in software. it is cleared in hard- ware at completion of the read operation. register 4-1: program memory read control register 1 (pmcon1: 18ch) 4.0.2 pmdath and pmdatl registers the pmdath:pmdatl registers are loaded with the contents of program memory addressed by the pmadrh and pmadrl registers upon completion of a program memory read command. r-1 u-0 u-0 u-0 u-0 u-0 u-0 r/s-0 reserved rd r = readable bit w = writable bit s = settable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: reserved: read as 1 bit 6-1: unimplemented: read as '0' bit 0: rd : read control bit 1 = initiates a program memory read (read takes 2 cycles. rd is cleared in hardware. 0 = reserved
pic16c717/770/771 ds41120a-page 44 advanced information ? 1999 microchip technology inc. register 4-2: program memory data high (pmdath: 10eh) register 4-3: program memory data low (pmdatl: 10ch) register 4-4: program memory address high (pmadrh: 10fh) register 4-5: program memory address low (pmadrl: 10dh) u-0 u-0 r-x r-x r-x r-x r-x r-x pmd13 pmd12 pmd11 pmd10 pmd9 pmd8 r = readable bit w = writable bit s = settable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-0: pmd<13:8>: the value of the program memory word pointed to by pmadrh and pmadrl after a program memory read command. r-x r-x r-x r-x r-x r-x r-x r-x pmd7 pmd6 pmd5 pmd4 pmd3 pmd2 pmd1 pmd0 r = readable bit w = writable bit s = settable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-0: pmd<7:0>: the value of the program memory word pointed to by pmadrh and pmadrl after a program memory read command. u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x pma11 pma10 pma9 pma8 r = readable bit w = writable bit s = settable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-4: unimplemented: read as '0' bit 3-0: pma<11:8>: pmr address bits r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x pma7 pma6 pma5 pma4 pma3 pma2 pma1 pma0 r = readable bit w = writable bit s = settable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-0: pma<7:0>: pmr address bits
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 45 4.0.3 reading the eprom program memory to read a program memory location, the user must write 2 bytes of the address to the pmadrh and pmadrl registers, then set control bit rd (pmcon1<0>). once the read control bit is set, the program memory read (pmr) controller will use the second instruction cycle after to read the data. this causes the second instruction immediately following the bsf pmcon1,rd instruction to be ignored. the data is available, in the very next cycle, in the pmdath and pmdatl registers; therefore it can be read as 2 bytes in the following instructions. pmdath and pmdatl registers will hold this value until another read or until it is written to by the user. example 4-1: otp program memory read bsf status, rp1 ; bcf status, rp0 ; bank 2 movlw ms_prog_pm_addr ; movwf pmadrh ; ms byte of program memory address to read movlw ls_prog_pm_addr ; movwf pmadrl ; ls byte of program memory address to read bsf status, rp0 ; bank 3 bsf pmcon1, rd ; program memory read nop ; this instruction is executed nop ; this instruction must be a nop next instruction ; pmdath:pmdatl now has the data 4.0.4 operation during code protect when the device is code protected, the cpu can still perform the program memory read function. figure 4-1: program memory read cycle execution q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bsf pmcon1,rd executed here instr(pc+1) executed here forced nop executed here pc pc+1 pmadrh,pmadrl pc+3 pc+5 program rd bit pc+3 pc+4 instr(pc-1) executed here instr(pc+3) executed here instr(pc+4) executed here pmdath pmdatl register memory addr
pic16c717/770/771 ds41120a-page 46 advanced information ? 1999 microchip technology inc. notes:
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 47 5.0 timer0 module the timer0 module timer/counter has the following fea- tures: ? 8-bit timer/counter ? readable and writable ? internal or external clock select ? edge select for external clock ? 8-bit software programmable prescaler ? interrupt on overflow from ffh to 00h figure 5-1 is a simplified block diagram of the timer0 module. additional information on timer modules is available in the picmicro? mid-range reference manual, (ds33023). 5.1 timer0 operation timer0 can operate as a timer or as a counter. timer mode is selected by clearing bit t0cs (option_reg<5>). in timer mode, the timer0 mod- ule will increment every instruction cycle (without pres- caler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option_reg<5>). in counter mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 source edge select bit t0se (option_reg<4>). clearing bit t0se selects the ris- ing edge. restrictions on the external clock input are discussed in below. when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. additional information on external clock requirements is available in the picmicro? mid-range reference manual, (ds33023). 5.2 pre scaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer, respectively ( figure 5-2 ). for simplicity, this counter is being referred to as prescaler throughout this data sheet. note that there is only one prescaler available which is mutually exclusively shared between the timer0 module and the watchdog timer. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer, and vice-versa. the prescaler is not readable or writable. the psa and ps<2:0> bits (option_reg<3:0>) determine the prescaler assignment and prescale ratio. clearing bit psa will assign the prescaler to the timer0 module. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. setting bit psa will assign the prescaler to the watch- dog timer (wdt). when the prescaler is assigned to the wdt, prescale values of 1:1, 1:2, ..., 1:128 are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g. clrf 1, movwf 1, bsf 1, x....etc .) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. figure 5-1: timer0 block diagram note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, but will not change the prescaler assignment. note 1: t0cs, t0se, psa, ps<2:0> (option_reg<5:0>). 2: the prescaler is shared with watchdog timer (refer to figure 5-2 for detailed block diagram). ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 psout (2 t cy delay) psout data bus 8 psa ps2, ps1, ps0 set interrupt flag bit t0if on overflow 3
pic16c717/770/771 ds41120a-page 48 advanced information ? 1999 microchip technology inc. 5.2.1 switching prescaler assignment the prescaler assignment is fully under software con- trol, i.e., it can be changed on-the-fly during program execution. 5.3 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h. this overflow sets bit t0if (intcon<2>). the interrupt can be masked by clearing bit t0ie (intcon<5>). bit t0if must be cleared in software by the timer0 module interrupt ser- vice routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep since the timer is shut off during sleep. figure 5-2: block diagram of the timer0/wdt prescaler table 5-1: registers associated with timer0 note: to avoid an unintended device reset, a specific instruction sequence (shown in the picmicro? mid-range reference man- ual, ds33023) must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is disabled. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 01h,101h tmr0 timer0 register xxxx xxxx uuuu uuuu 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h,181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa porta data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0. ra4/t0cki t0se pin m u x clkout (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps<2:0> 8 note: t0cs, t0se, psa, ps<2:0> are (option_reg<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set flag bit t0if on overflow 8 psa t0cs
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 49 6.0 timer1 module the timer1 module timer/counter has the following fea- tures: ? 16-bit timer/counter (two 8-bit registers; tmr1h and tmr1l) ? readable and writable (both registers) ? internal or external clock select ? interrupt on overflow from ffffh to 0000h ? reset from eccp module trigger timer1 has a control register, shown in register 6-1 . timer1 can be enabled/disabled by setting/clearing control bit tmr1on (t1con<0>). figure 6-2 is a simplified block diagram of the timer1 module. additional information on timer modules is available in the picmicro? mid-range reference manual, (ds33023). 6.1 timer1 operation timer1 can operate in one of these modes: ?as a timer ? as a synchronous counter ? as an asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input. when the timer1 oscillator is enabled (t1oscen is set), the rb7/t1osi/p1d and rb6/t1oso/t1cki/ p1c pins are no longer available as i/o ports or pwm outputs. that is, the trisb<7:6> value is ignored. timer1 also has an internal reset input. this reset can be generated by the eccp module ( section 7.0 ). register 6-1: timer1 control register (t1con: 10h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: t1ckps<1:0>: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3: t1oscen: timer1 oscillator enable control bit 1 = oscillator is enabled 0 = oscillator is shut off note: the oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2: t1sync : timer1 external clock input synchronization control bit tmr1cs = 1 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0 this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1: tmr1cs: timer1 clock source select bit 1 = external clock from pin rb6/t1oso/t1cki /p1c(on the rising edge) 0 = internal clock (f osc /4) bit 0: tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1
pic16c717/770/771 ds41120a-page 50 advanced information ? 1999 microchip technology inc. 6.1.1 timer1 counter operation in this mode, timer1 is being incremented via an exter- nal source. increments occur on a rising edge. after timer1 is enabled in counter mode, the module must first have a falling edge before the counter begins to increment. figure 6-1: timer1 incrementing edge figure 6-2: timer1 block diagram t1cki (initially high) t1cki (initially low) note: arrows indicate counter increments. first falling edge of the t1on enabled first falling edge of the t1on enabled tmr1h tmr1l t1osc t1sync tmr1cs t1ckps<1:0> sleep input t1oscen enable oscillator (1) f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 rb6/t1oso/t1cki/p1c rb7/t1osi/p1d note 1: when the t1oscen bit is cleared, the inverter and feedback resistor are turned off. this eliminates power drain. set flag bit tmr1if on overflow tmr1
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 51 6.2 timer1 oscillator a crystal oscillator circuit is built in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con<3>). the oscilla- tor is a low power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for a 32 khz crystal. ta b l e 6 - 1 shows the capacitor selection for the timer1 oscillator. the timer1 oscillator is identical to the lp oscillator. the user must provide a software time delay to ensure proper oscillator start-up. table 6-1: capacitor selection for the timer1 oscillator 6.3 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clear- ing tmr1 interrupt enable bit tmr1ie (pie1<0>). 6.4 resetting timer1 using a ccp trigger output if the eccp module is configured in compare mode to generate a special event trigger" (ccp1m<3:0> = 1011 ), this signal will reset timer1 and start an a/d conversion (if the a/d module is enabled). timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a spe- cial event trigger from eccp1, the write will take prece- dence. in this mode of operation, the ccpr1h:ccpr1l regis- ters pair effectively becomes the period register for timer1. table 6-2: registers associated with timer1 as a timer/counter osc type freq c1 c2 lp 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf these values are for design guidance only. note 1: higher capacitance increases the stability of oscillator but also increases the start-up time. 2: since each resonator/crystal has its own charac- teristics, the user should consult the resonator/ crystal manufacturer for appropriate values of external components. note: the special event triggers from the ccp1 module will not set interrupt flag bit tmr1if (pir1<0>). address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer1 module.
pic16c717/770/771 ds41120a-page 52 advanced information ? 1999 microchip technology inc. notes:
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 53 7.0 timer2 module the timer2 module timer has the following features: ? 8-bit timer (tmr2 register) ? 8-bit period register (pr2) ? readable and writable (both registers) ? software programmable prescaler (1:1, 1:4, 1:16) ? software programmable postscaler (1:1 to 1:16) ? interrupt on tmr2 match of pr2 ? ssp module optional use of tmr2 output to gen- erate clock shift timer2 has a control register, shown in register 7-1 . timer2 can be shut off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. figure 7-1 is a simplified block diagram of the timer2 module. additional information on timer modules is available in the picmicro? mid-range reference manual, (ds33023). 7.1 timer2 operation timer2 can be used as the pwm time-base for pwm mode of the eccp module. the tmr2 register is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps<1:0> (t2con<1:0>). the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if, (pir1<1>)). the prescaler and postscaler counters are cleared when any of the following occurs: ? a write to the tmr2 register ? a write to the t2con register ? any device reset (power-on reset, mclr reset, watchdog timer reset, or brown-out reset) tmr2 is not cleared when t2con is written. register 7-1: timer2 control register (t2con1: 12h) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6-3: toutps<3:0>: timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale ? ? ? 1111 = 1:16 postscale bit 2: tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0: 2ckps<1:0>: timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16
pic16c717/770/771 ds41120a-page 54 advanced information ? 1999 microchip technology inc. 7.2 timer2 interrupt the timer2 module has an 8-bit period register pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is ini- tialized to ffh upon reset. 7.3 output of tmr2 the output of tmr2 (before the postscaler) is fed to the synchronous serial port module which optionally uses it to generate shift clock. figure 7-1: timer2 block diagram table 7-1: registers associated with timer2 as a timer/counter comparator tmr2 sets flag tmr2 reg output (1) reset postscaler prescaler pr2 reg 2 f osc /4 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. to address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 11h tmr2 timer2 register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer2 module.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 55 8.0 enhanced capture/ compare/pwm(eccp) modules the eccp (enhanced capture/compare/pwm) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a pwm master/slave duty cycle register. ta bl e 8 - 1 shows the timer resources of the eccp mod- ule modes. capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con and p1del reg- isters control the operation of eccp. all are readable and writable. register 8-1: ccp1 control register (ccp1con: 17h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pwm1m1 pwm1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 r = readable bit w= writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-6: pwm1m<1:0>: pwm output configuration if ccp1m<3:2> = 00, 01, 10 xx - p1a assigned as capture/compare input. p1b, p1c, p1d assigned as port pins. if ccp1m<3:2> = 11 00 - single output. p1a modulated. p1b, p1c, p1d assigned as port pins. 01 - full-bridge output forward. p1d modulated. p1a active. p1b, p1c inactive. 10 - half-bridge output. p1a, p1b modulated with deadband control. p1c, p1d assigned as port pins. 11 - full-bridge output reverse. p1b modulated. p1c active. p1a, p1d inactive. bit 5-4: dc1b<1:0>: pwm duty cycle least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprnl. bit 3-0: ccp1m<3:0>: eccp1 mode select bits 0000 = capture/compare/pwm off (resets eccp module) 0001 = unused (reserved) 0010 = compare mode, toggle output on match (ccp1if bit is set) 0011 = unused (reserved) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccp1if bit is set) 1001 = compare mode, clear output on match (ccp1if bit is set) 1010 = compare mode, generate software interrupt on match (ccp1if bit is set, ccp1 pin is unaffected) 1011 = compare mode, trigger special event (ccp1if bit is set; eccp resets tmr1, and starts an a/d conversion, if the a/d module is enabled.) 1100 = pwm mode. p1a, p1c active high. p1b, p1d active high. 1101 = pwm mode. p1a, p1c active high. p1b, p1d active low. 1110 = pwm mode. p1a, p1c active low. p1b, p1d active high. 1111 = pwm mode. p1a, p1c active low. p1b, p1d active low.
pic16c717/770/771 ds41120a-page 56 advanced information ? 1999 microchip technology inc. table 8-1: eccp mode - timer resource 8.1 capture mode in capture mode, ccpr1h:ccpr1l captures the 16- bit value of the tmr1 register when an event occurs on pin ccp1. an event is defined as: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge an event is selected by control bits ccp1m<3:0> (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit ccp1if (pir1<2>) is set. it must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value will be lost. 8.1.1 ccp1 pin configuration in capture mode, the ccp1 pin should be configured as an input by setting the trisb<3> bit. 8.1.2 timer1 mode selection timer1 must be running in timer mode or synchronized counter mode. in asynchronous counter mode, the capture operation may not work. 8.1.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<2>) clear to avoid false interrupts and should clear the flag bit ccp1if following any such change in operating mode. 8.1.4 eccp prescaler there are four prescaler settings, specified by bits ccp1m<3:0>. whenever the eccp module is turned off or the eccp1 module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore the first capture may be from a non-zero prescaler. example 8-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the false interrupt. example 8-1: changing between capture prescalers clrf ccp1con, f ; turn eccp module off movlw new_capt_ps ; load wreg with the ; new prescaler mode ; value and eccp on movwf ccp1con ; load ccp1con with ; this value figure 8-1: capture mode operation block diagram 8.2 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the ccp1 pin is: ?driven high ? driven low ? toggle output (high to low or low to high) ? remains unchanged the action on the pin is based on the value of control bits ccp1m<3:0>. at the same time, interrupt flag bit ccp1if is set. 8.2.1 ccp1 pin configuration the user must configure the ccp1 pin as an output by clearing the appropriate trisb bit. 8.2.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode if the eccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 8.2.3 software interrupt mode when generate software interrupt is chosen, the ccp1 pin is not affected. only an eccp interrupt is generated (if enabled). eccp1 mode timer resource capture compare pwm timer1 timer1 timer2 note: if the rb3/ccp1/p1a pin is configured as an output, a write to the port can cause a capture condition. note: clearing the ccp1con register will force the ccp1 compare output latch to the default low level. this is not the port data latch. ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<2>) capture enable qs ccp1con<3:0> rb3/ccp1/ prescaler ? 1, 4, 16 and edge detect p1a pin
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 57 8.2.4 special event trigger in this mode, an internal hardware trigger is generated, which may be used to initiate an action. the special event trigger output of eccp resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special event trigger output of eccp module will also start an a/d conversion if the a/d module is enabled. figure 8-2: compare mode operation block diagram table 8-2: registers associated with capture, compare and timer1 note: the special event trigger will not set the interrupt flag bit tmr1if (pir1<0>). ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if (pir1<2>) match rb3/ccp1/ trisb<3> ccp1con<3:0> mode select output enable p1a pin special event trigger will: reset timer1, but not set interrupt flag bit tmr1if (pir1<0>). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 trisb portb data direction register 1111 1111 1111 1111 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1register xxxx xxxx uuuu uuuu t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu ccp1con pwm1m1 pwm1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by capture and timer1.
pic16c717/770/771 ds41120a-page 58 advanced information ? 1999 microchip technology inc. 8.3 pwm mode in pulse width modulation (pwm) mode, the eccp module produces up to a 10-bit resolution pwm output. figure 8-3 shows the simplified pwm block diagram. figure 8-3: simplified pwm block diagram 8.3.1 pwm period the pwm period is specified by writing to the pr2 reg- ister. the pwm period can be calculated using the fol- lowing formula: pwm period = (pr2) + 1] ? 4 ? t osc ? (tmr2 prescale value ) pwm frequency is defined as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ? tmr2 is cleared ? the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) ? the pwm duty cycle is latched from ccpr1l into ccpr1h ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. note: 8-bit timer tmr2 is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time-base. trisb<3> rb3/ccp1/p1a trisb<5> rb5/sdo/p1b trisb<6> rb6/t1oso/t1cki/ trisb<7> rb7/t1osi/p1d p1c output controller pwm1m1<1:0> 2 ccp1m<3:0> 4 p1del ccp1/p1a p1b p1c p1d note: the timer2 postscaler (see section 7.0 ) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different fre- quency than the pwm output.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 59 8.3.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: pwm duty cycle = (ccpr1l:ccp1con<5:4>) ? t osc ? (tmr2 prescale value) ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2 con- catenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. maximum pwm resolution (bits) for a given pwm fre- quency: 8.3.3 pwm output configurations the pwm1m1 bits in the ccp1con register allows one of the following configurations: ? single output ? half-bridge output ? full-bridge output, forward mode ? full-bridge output, reverse mode in the single output mode, the rb3/ccp1/p1a pin is used as the pwm output. since the ccp1 output is multiplexed with the portb<3> data latch, the trisb<3> bit must be cleared to make the ccp1 pin an output. figure 8-4: single pwm output figure 8-5: example of single output application in the half-bridge output mode, two pins are used as outputs. the rb3/ccp1/p1a pin has the pwm output signal, while the rb5/sdo/p1b pin has the comple- mentary pwm output signal. this mode can be used for half-bridge applications, as shown on figure 8-7 , or for full-bridge applications, where four power switches are being modulated with two pwm signal. since the p1a and p1b outputs are multiplexed with the portb<3> and portb<5> data latches, the trisb<3> and trisb<5> bits must be cleared to con- figure p1a and p1b as outputs. in half-bridge output mode, the programmable dead- band delay can be used to prevent shoot-through cur- rent in bridge power devices. see section 8.3.5 for more details of the deadband delay operations. note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. f osc f pwm --------------- ? ?? log 2 () log ----------------------------- bits = period duty cycle (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. ccp1 (2) 2: output signal is shown as asserted high. c pic16c717/770/771 ccp1 r v out using pwm as a d/a converter pic16c717/770/771 ccp1 using pwm to drive a power v+ l o a d load
pic16c717/770/771 ds41120a-page 60 advanced information ? 1999 microchip technology inc. 8.3.4 output polarity configuration the ccp1m<1:0> bits in the ccp1con register allow user to choose the logic conventions (asserted high/ low) for each of the outputs. see register 8-1 for fur- ther details. the pwm output polarities must be selected before the pwm outputs are enabled. charging the polarity con- figuration while the pwm outputs are active is not rec- ommended, since it may result in unpredictable operation. figure 8-6: half-bridge pwm output note 1: at this time, the tmr2 register is equal to the pr2 register. period duty cycle td td (1) p1a (2) p1b (2) td = deadband delay period (1) (1) 2: output signals are shown as asserted high.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 61 figure 8-7: example of half-bridge output mode applications pic16c717/770/771 p1a p1b fet driver fet driver v+ v- load + - + v - + v - pic16c717/770/771 p1a p1b fet driver fet driver v+ v- load + - fet driver fet driver
pic16c717/770/771 ds41120a-page 62 advanced information ? 1999 microchip technology inc. in full-bridge output mode, four pins are used as out- puts; however, only two outputs are active at a time. in the forward mode, rb3/ccp1/p1a pin is continuously active, and rb7/t1osi/p1d pin is modulated. in the reverse mode, rb6/t1oso/t1cki/p1c pin is contin- uously active, and rb5/sdo/p1b pin is modulated. p1a, p1b, p1c and p1d outputs are multiplexed with portb<3> and portb<5:7> data latches. trisb<3> and trisb<5:7> bits must be cleared to make the p1a, p1b, p1c, and p1d pins output. figure 8-8: full-bridge pwm output period duty cycle p1a (2) p1b (2) p1c (2) p1d (2) forward mode (1) period duty cycle p1a (2) p1c (2) p1d (2) p1b (2) reverse mode 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (1) (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. 2: output signal is shown as asserted high.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 63 figure 8-9: example of full-bridge application pic16c717/770/771 p1d p1a fet driver fet driver v+ v- load + - fet driver fet driver p1c p1b
pic16c717/770/771 ds41120a-page 64 advanced information ? 1999 microchip technology inc. 8.3.5 programmable deadband delay in half-bridge or full-bridge applications, where all power switches are modulated at the pwm frequency at all time, the power switches normally require longer time to turn off than to turn on. if both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches will be on for a short period of time, until one switch completely turns off. during this time, a very high cur- rent, called shoot-through current, will flow through both power switches, shorting the bridge supply. to avoid this potentially destructive shoot-through current from flowing during switching, turning on the power switch is normally delayed to allow the other switch to completely turn off. in the half-bridge output mode, a digitally program- mable deadband delay is available to avoid shoot- through current from destroying the bridge power switches. the delay occurs at the signal transition from the non-active state to the active state. see figure 8-6 for illustration. the p1del register sets the amount of delay. register 8-2: pwm delay register (p1del: 97h) 8.3.6 direction change in full-bridge output mode in the full-bridge output mode, the pwm1m1 bit in the ccp1con register allows user to control the forward/ reverse direction. when the application firmware changes this direction control bit, the eccp module will assume the new direction on the next pwm cycle. the current pwm cycle still continues, however, the non- modulated outputs, p1a and p1c signals, will transition to the new direction tosc, 4 tosc or 16 tosc (for timer2 presale t2ckrs<1:0> = 00, 01 and 1x respec- tively) earlier, before the end of the period. during this transition cycle, the modulated outputs, p1b and p1d, will go to the inactive state. see figure 8-10 for illustra- tion. figure 8-10: pwm direction change r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-0: p1del<7:0>: pwm delay count for half-bridge output mode: number of f osc /4 (tosc 4) cycles between the p1a transition and the p1b transition. dc period signal p1a (active high) p1b (active high) p1c (active high) p1d (active high) note 1: the direction bit in the eccp control register (ccp1con.pwm1m1) is written anytime during the pwm cycle. 2: the p1a and p1c signals switch t osc , 4*tosc or 16*t osc depending on the timer2 prescaler value earlier when changing direction. the modulated p1b and p1d signals are inactive at this time. (1) period (2)
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 65 note that in the full-bridge output mode, the eccp module does not provide any deadband delay. in gen- eral, since only one output is modulated at all time, deadband delay is not required. however, there is a sit- uation where a deadband delay might be required. this situation occurs when all of the following conditions are true: 1. the direction of the pwm output changes when the duty cycle of the output is at or near 100%. 2. the turn off time of the power switch, including the power device and driver circuit, is greater than turn on time. figure 8-11 shows an example, where the pwm direc- tion changes from forward to reverse at a near 100% duty cycle. at time t1, the output p1a and p1d become inactive, while output p1c becomes active. in this example, since the turn off time of the power devices is longer than the turn on time, a shoot-through current flows through the power devices, qb and qd, for the duration of t= t off -t on . the same phenomenon will occur to power devices, qc and qb, for pwm direction change from reverse to forward. if changing pwm direction at high duty cycle is required for the users application, one of the following require- ments must be met: 1. avoid changing pwm output direction at or near 100% duty cycle. 2. use switch drivers that compensate the slow turn off of the power devices. the total turn off time (t off ) of the power device and the driver must be less than the turn on time (t on ). figure 8-11: pwm direction change at near 100% duty cycle forward period reverse period (pwm) p1a 1 0 (pwm) t on t off t = t off - t on 1 0 1 0 1 0 1 0 1 0 1 0 p1b p1c p1d external switch d potential shoot through current note 1: all signals are shown as active high. 2: t on is the turn on delay of power switch and driver. 3: t off is the turn off delay of power switch and driver. external switch c t 1
pic16c717/770/771 ds41120a-page 66 advanced information ? 1999 microchip technology inc. 8.3.7 system implementation when the eccp module is used in the pwm mode, the application hardware must use the proper external pull- up and/or pull-down resistors on the pwm output pins. when the microcontroller powers up, all of the i/o pins are in the high-impedance state. the external pull-up and pull-down resistors must keep the power switch devices in the off state until the microcontroller drives the i/o pins with the proper signal levels, or activates the pwm output(s). 8.3.8 start-up considerations prior to enabling the pwm outputs, the p1a, p1b, p1c and p1d latches may not be in the proper states. enabling the trisb bits for output at the same time with the ccp module may cause damage to the power switch devices. the ccp1 module must be enabled in the proper output mode with the trisb bits enabled as inputs. once the ccp1 completes a full pwm cycle, the p1a, p1b, p1c and p1d output latches are properly initialized. at this time, the trisb bits can be enabled for outputs to start driving the power switch devices. the completion of a full pwm cycle is indicated by the tmr2if bit going from a '0' to a '1'. 8.3.9 set up for pwm operation the following steps should be taken when configuring the eccp module for pwm operation: 1. configure the pwm module: a) disable the ccp1/p1a, p1b, p1c and/or p1d outputs by setting the respective trisb bits. b) set the pwm period by loading the pr2 register. c) set the pwm duty cycle by loading the ccpr1l register and ccp1con<5:4> bits. d) configure the eccp module for the desired pwm operation by loading the ccp1con register. with the ccp1m<3:0> bits select the active high/low levels for each pwm output. with the pwm1m<1:0> bits select one of the available output modes: single, half-bridge, full-bridge, forward or full- bridge reverse. e) for half-bridge output mode, set the dead- band delay by loading the p1del register. 2. configure and start tmr2: a) clear the tmr2 interrupt flag bit by clearing the tmr2if bit in the pir1 register. b) set the tmr2 prescale value by loading the t2ckps<1:0> bits in the t2con register. c) enable timer2 by setting the tmr2on bit in the t2con register. 3. enable pwm outputs after a new cycle has started: a) wait until tmr2 overflows (tmr2if bit becomes a 1). the new pwm cycle begins here. b) enable the ccp1/p1a, p1b, p1c and/or p1d pin outputs by clearing the respective trisb bits. table 8-3: registers associated with pwm address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh, 10bh, 18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 86h, 186h trisb portb data direction register 1111 1111 1111 1111 11h tmr2 timer2 register 0000 0000 0000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 17h ccp1con pwm1m1 pwm1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 97h p1del pwm1 delay value 0000 0000 0000 0000 legend: legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by capture and timer1.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 67 9.0 master synchronous serial port (mssp) module the master synchronous serial port (mssp) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, etc. the mssp module can operate in one of two modes: ? serial peripheral interface (spi?) ? inter-integrated circuit (i 2 c?)
pic16c717/770/771 ds41120a-page 68 advanced information ? 1999 microchip technology inc. register 9-1: sync serial port status register (sspstat: 94h) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: smp : sample bit spi master mode 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode smp must be cleared when spi is used in slave mode in i 2 c master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high speed mode (400 khz) bit 6: cke: spi clock edge select ( figure 9-3 , figure 9-5 , and figure 9-6 ) ckp = 0 1 = data transmitted on rising edge of sck 0 = data transmitted on falling edge of sck ckp = 1 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck bit 5: d/a: data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4: p: stop bit (i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit was not detected last bit 3: s: start bit (i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared) 1 = indicates that a start bit has been detected last (this bit is '0' on reset) 0 = start bit was not detected last bit 2: r/w: read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or not ack bit. in i 2 c slave mode: 1 = read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress. oring this bit with sen, rsen, pen, rcen, or aken will indicate if the mssp is in idle mode bit 1: ua: update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0: bf: buffer full status bit receive (spi and i 2 c modes) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit (i 2 c mode only) 1 = data transmit in progress (does not include the ack and stop bits), sspbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspbuf is empty
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 69 register 9-2: sync serial port control register (sspcon: 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 r = readable bit w = writable bit - n = value at por reset bit7 bit0 bit 7: wcol: write collision detect bit master mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started 0 = no collision slave mode: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6: sspov: receive overflow indicator bit in spi mode 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. in slave mode, the user must read the sspbuf, even if only transmitting data, to avoid setting overflow. in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. (must be cleared in software). 0 = no overflow in i 2 c mode 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a "dont care" in transmit mode. (must be cleared in software). 0 = no overflow bit 5: sspen: synchronous serial port enable bit in both modes, when enabled, these pins must be properly configured as input or output. in spi mode 1 = enables serial port and configures sck, sdo, sdi, and ss as the source of the serial port pins 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode 1 = enables the serial port and configures the sda and scl pins as the source of the serial port pins 0 = disables serial port and configures these pins as i/o port pins bit 4: ckp: clock polarity select bit in spi mode 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c slave mode sck release control 1 = enable clock 0 = holds clock low (clock stretch) (used to ensure data setup time) in i 2 c master mode unused in this mode bit 3-0: sspm<3:0>: synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = i 2 c master mode, clock = f osc / (4 (sspadd+1) ) 1xx1 = reserved 1x1x = reserved
pic16c717/770/771 ds41120a-page 70 advanced information ? 1999 microchip technology inc. register 9-3: sync serial port control register2 (sspcon2: 91h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt acken rcen pen rsen sen r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: gcen: general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address (0000h) is received in the sspsr. 0 = general call address disabled. bit 6: ackstat: acknowledge status bit (in i 2 c master mode only) in master transmit mode: 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5: ackdt: acknowledge data bit (in i 2 c master mode only) in master receive mode: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. 1 = not acknowledge 0 = acknowledge bit 4: acken: acknowledge sequence enable bit (in i 2 c master mode only). in master receive mode: 1 = initiate acknowledge sequence on sda and scl pins, and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3: rcen: receive enable bit (in i 2 c master mode only). 1 = enables receive mode for i 2 c 0 = receive idle bit 2: pen: stop condition enable bit (in i 2 c master mode only). sck release control 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1: rsen: repeated start condition enabled bit (in i 2 c master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle. bit 0: sen: start condition enabled bit (in i 2 c master mode only) 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle. note: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled).
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 71 9.1 spi mode the spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. all four modes of spi are supported. to accomplish communi- cation, typically three pins are used: ? serial data out (sdo) ? serial data in (sdi) ? serial clock (sck) additionally, a fourth pin may be used when in a slave mode of operation: ?slave select (ss ) 9.1.1 operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspcon<5:0> and sspstat<7:6>). these control bits allow the following to be specified: ? master mode (sck is the clock output) ? slave mode (sck is the clock input) ? clock polarity (idle state of sck) ? data input sample phase (middle or end of data output time) ? clock edge (output data on rising/falling edge of sck) ? clock rate (master mode only) ? slave select mode (slave mode only) figure 9-1 shows the block diagram of the mssp mod- ule when in spi mode. figure 9-1: mssp block diagram (spi mode) the mssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr, until the received data is ready. once the 8 bits of data have been received, that byte is moved to the sspbuf register. then the buffer full detect bit, bf (sspstat<0>), and the interrupt flag bit, sspif (pir1<3>), are set. this double buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored, and the write collision detect bit wcol (sspcon<7>) will be set. user software must clear the wcol bit so that it can be determined if the following write(s) to the ssp- buf register completed successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. buffer full bit, bf (sspstat<0>), indicates when the ssp- buf has been loaded with the received data (transmis- sion is complete). when the sspbuf is read, bit bf is cleared. this data may be irrelevant if the spi is only a transmitter. generally the mssp interrupt is used to read write internal data bus sspsr reg sspbuf reg sspm<3:0> bit0 shift clock ss control enable edge select clock select tmr2 output to s c prescaler 4, 16, 64 2 edge select 2 4 data to tx/rx in sspsr data direction bit 2 smp:cke sdi sdo ss sck
pic16c717/770/771 ds41120a-page 72 advanced information ? 1999 microchip technology inc. determine when the transmission/reception has com- pleted. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 9-1 shows the loading of the sspbuf (sspsr) for data transmission. example 9-1: loading the sspbuf (sspsr) register the sspsr is not directly readable or writable, and can only be accessed by addressing the sspbuf register. additionally, the mssp status register (sspstat) indi- cates the various status conditions. 9.1.2 enabling spi i/o to enable the serial port, mssp enable bit, sspen (sspcon<5>) must be set. to reset or reconfigure spi mode, clear bit sspen, re-initialize the sspcon reg- isters, and then set bit sspen. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port function, some must have their data direction bits (in the tris register) appropriately programmed. that is: ? sdi is automatically controlled by the spi module ? sdo must have trisb<5> cleared ? sck (master mode) must have trisb<2> cleared ? sck (slave mode) must have trisb<2> set ?ss must have trisb<1> set, and ansel<5> cleared any serial port function that is not desired may be over- ridden by programming the corresponding data direc- tion (tris) register to the opposite value. 9.1.3 typical connection figure 9-2 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their pro- grammed clock edge, and latched on the opposite edge of the clock. both processors should be programmed to same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: ? master sends data slave sends dummy data ? master sends data slave sends data ? master sends dummy data slave sends data figure 9-2: spi master/slave connection bsf status, rp0 ;specify bank 1 loop btfss sspstat, bf ;has data been ;received ;(transmit ;complete)? goto loop ;no bcf status, rp0 ;specify bank 0 movf sspbuf, w ;w reg = contents ;of sspbuf movwf rxdata ;save in user ram movf txdata, w ;w reg = contents ; of txdata movwf sspbuf ;new data to xmit serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm<3:0> = 00xxb serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm<3:0> = 010xb serial clock
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 73 9.1.4 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2, figure 9-2 ) is to broad- cast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspbuf register is written to. if the spi module is only going to receive, the sdo output could be disabled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a line activity monitor. the clock polarity is selected by appropriately program- ming bit ckp (sspcon<4>). this then would give waveforms for spi communication as shown in figure 9-3 , figure 9-5 and figure 9-6 , where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the follow- ing: ?f osc /4 (or t cy ) ?f osc /16 (or 4 ? t cy ) ?f osc /64 (or 16 ? t cy ) ? timer2 output/2 this allows a maximum bit clock frequency (at 20 mhz) of 8.25 mhz. figure 9-3 shows the waveforms for master mode. when cke = 1, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 9-3: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit0 sdi sspif (smp = 1) (smp = 0) (smp = 1) cke = 1) cke = 0) cke = 1) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (cke = 0) (cke = 1) next q4 cycle after q2
pic16c717/770/771 ds41120a-page 74 advanced information ? 1999 microchip technology inc. 9.1.5 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched the interrupt flag bit sspif (pir1<3>) is set. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. when a byte is received, the device will wake-up from sleep. 9.1.6 slave select synchronization the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon<3:0> = 0100 ). the pin must not be driven low for the ss pin to function as an input. trisb<1> must be set. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. external pull-up/ pull-down resistors may be desirable, depending on the application. when the spi module resets, the bit counter is forced to 0. this can be done by either forcing the ss pin to a high level or clearing the sspen bit. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver, the sdo pin can be configured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus conflict. figure 9-4: slave synchronization waveform note 1: when the spi module is in slave mode with ss pin control enabled, (ssp- con<3:0> = 0100 ) the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke = '1', then ss pin control must be enabled. sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 sdo bit7 bit6 bit7 sspif interrupt (smp = 0) cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss flag bit0 bit7 bit0 next q4 cycle after q2?
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 75 figure 9-5: spi slave mode waveform (cke = 0) figure 9-6: spi slave mode waveform (cke = 1) sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif interrupt (smp = 0) cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss flag optional next q4 cycle after q2? sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif interrupt (smp = 0) cke = 1) cke = 1) (smp = 0) write to sspbuf sspsr to sspbuf ss flag not optional next q4 cycle after q2?
pic16c717/770/771 ds41120a-page 76 advanced information ? 1999 microchip technology inc. 9.1.7 sleep operation in master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from sleep. after the device returns to normal mode, the module will continue to transmit/ receive data. in slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode and data to be shifted into the spi transmit/receive shift register. when all 8 bits have been received, the mssp interrupt flag bit will be set and if enabled will wake the device from sleep. 9.1.8 effects of a reset a reset disables the mssp module and terminates the current transfer. table 9-1: registers associated with spi operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 por, bor mclr , wdt 0bh, 8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 94h sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the mssp in spi mode.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 77 9.2 mssp i 2 c operation the mssp module in i 2 c mode fully implements all master and slave functions (including general call sup- port) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master func- tion). the mssp module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. refer to application note an578, "use of the ssp module in the i 2 c multi-master environment." a "glitch" filter is on the scl and sda pins when the pin is an input. this filter operates in both the 100 khz and 400 khz modes. in the 100 khz mode, when these pins are an output, there is a slew rate control of the pin that is independent of device frequency. figure 9-7: i 2 c slave mode block diagram figure 9-8: i 2 c master mode block diagram two pins are used for data transfer. these are the scl pin, which is the clock, and the sda pin, which is the data. the mssp module functions are enabled by set- ting ssp enable bit sspen (sspcon<5>). the mssp module has six registers for i 2 c operation. they are the: ? ssp control register (sspcon) ? ssp control register2 (sspcon2) ? ssp status register (sspstat) ? serial receive/transmit buffer (sspbuf) ? ssp shift register (sspsr) - not directly acces- sible ? ssp address register (sspadd) the sspcon register allows control of the i 2 c opera- tion. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: ?i 2 c slave mode (7-bit address) ?i 2 c slave mode (10-bit address) ?i 2 c master mode, clock = osc/4 (sspadd +1) before selecting any i 2 c mode, the scl and sda pins must be programmed to inputs by setting the appropri- ate tris bits. selecting an i 2 c mode, by setting the sspen bit, enables the scl and sda pins to be used as the clock and data lines in i 2 c mode. the sspstat register gives the status of the data transfer. this information includes detection of a start (s) or stop (p) bit, specifies if the received byte was data or address if the next byte is the comple- tion of 10-bit address, and if this will be a read or write data transfer. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) scl shift clock msb lsb sda read write sspsr reg match detect sspadd reg start and stop bit detect / generate sspbuf reg internal data bus addr match set/clear s bit clear/set p bit (sspstat reg) scl shift clock msb lsb sda baud rate generator 7 sspadd<6:0> and and set sspif
pic16c717/770/771 ds41120a-page 78 advanced information ? 1999 microchip technology inc. sspbuf is the register to which the transfer data is written to or read from. the sspsr register shifts the data in or out of the device. in receive operations, the sspbuf and sspsr create a doubled buffered receiver. this allows reception of the next byte to begin before reading the last byte of received data. when the complete byte is received, it is transferred to the sspbuf register and flag bit sspif is set. if another complete byte is received before the sspbuf register is read, a receiver overflow has occurred and bit sspov (sspcon<6>) is set and the byte in the sspsr is lost. the sspadd register holds the slave address. in 10-bit mode, the user needs to write the high byte of the address ( 1111 0 a9 a8 0 ). following the high byte address match, the low byte of the address needs to be loaded (a7:a0). 9.2.1 slave mode in slave mode, the scl and sda pins must be config- ured as inputs. the mssp module will override the input state with the output data when required (slave- transmitter). when an address is matched or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse, and then load the sspbuf register with the received value currently in the sspsr register. there are certain conditions that will cause the mssp module not to give this ack pulse. these are if either (or both): a) the buffer full bit bf (sspstat<0>) was set before the transfer was received. b) the overflow bit sspov (sspcon<6>) was set before the transfer was received. if the bf bit is set, the sspsr register value is not loaded into the sspbuf, but bit sspif and sspov are set. ta bl e 9 - 2 shows what happens when a data trans- fer byte is received, given the status of bits bf and sspov. the shaded cells show the condition where user software did not properly clear the overflow condi- tion. flag bit bf is cleared by reading the sspbuf reg- ister while bit sspov is cleared through software. the scl clock input must have a minimum high and low time for proper operation. the high and low times of the i 2 c specification as well as the requirement of the mssp module is shown in timing parameter #100 and parameter #101 of the electrical specifications. 9.2.1.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start con- dition, the 8-bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register on the falling edge of the 8th scl pulse. b) the buffer full bit, bf is set on the falling edge of the 8th scl pulse. c) an ack pulse is generated. d) ssp interrupt flag bit, sspif (pir1<3>) is set (interrupt is generated if enabled) - on the falling edge of the 9th scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address the first byte would equal 1111 0 a9 a8 0 , where a9 and a8 are the two msbs of the address. the sequence of events for a 10-bit address is as follows, with steps 7- 9 for slave-transmit- ter: 1. receive first (high) byte of address (bits sspif, bf, and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf, and ua are set). 5. update the sspadd register with the first (high) byte of address. this will clear bit ua and release the scl line. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif. note: following the repeated start condition (step 7) in 10-bit mode, the user only needs to match the first 7-bit address. the user does not update the sspadd for the second half of the address.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 79 9.2.1.2 slave reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte overflow condition exists, then no acknowledge (ack ) pulse is given. an overflow con- dition is defined as either bit bf (sspstat<0>) or bit sspov (sspcon<6>) and is set. a mssp interrupt is generated for each data transfer byte. flag bit sspif (pir1<3>) must be cleared in soft- ware. the sspstat register is used to determine the status of the received byte. table 9-2: data transfer received byte actions 9.2.1.3 slave transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit, and the scl pin is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then the scl pin should be enabled by setting bit ckp (ssp- con<4>). the master must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretching the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time ( figure 9-10 ). a mssp interrupt is generated for each data transfer byte. the sspif flag bit must be cleared in software, and the sspstat register is used to determine the sta- tus of the byte transfer. the sspif flag bit is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the ack pulse from the master- receiver is latched on the rising edge of the ninth scl input pulse. if the sda line was high (not ack ), then the data transfer is complete. when the not ack is latched by the slave, the slave logic is reset and the slave then monitors for another occurrence of the start bit. if the sda line was low (ack ), the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then the scl pin should be enabled by setting the ckp bit. note: the sspbuf will be loaded if the sspov bit is set and the bf flag is cleared. if a read of the sspbuf was performed, but the user did not clear the state of the sspov bit before the next receive occurred, the ack is not sent and the ssp- buf is updated. status bits as data transfer is received sspsr ? sspbuf generate ack pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 yes yes yes 1 0 no no yes 1 1 no no yes 0 1 ye s no ye s note 1: shaded cells show the conditions where the user software did not properly clear the overflow condition.
pic16c717/770/771 ds41120a-page 80 advanced information ? 1999 microchip technology inc. figure 9-9: i 2 c waveforms for reception (7-bit address) figure 9-10: i 2 c waveforms for transmission (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read ack receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 ack r/w=0 receiving address sspif bf (sspstat<0>) sspov (sspcon<6>) ack ack is not sent. not sda scl sspif bf (sspstat<0>) ckp (sspcon<4>) a7 a6 a5 a4 a3 a2 a1 ack d7 d6 d5 d4 d3 d2 d1 d0 not ack transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written-to before the ckp bit can be set) r/w = 0
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 81 figure 9-11: i 2 c slave-transmitter (10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 789 1 2345 67 89 1 2345 789 p 1 111 0a9a8 a7 a6a5a4a3a2a1a0 11110 a8 r/w=1 ack ack r/w = 0 ack receive first byte of address cleared in software master sends nack a9 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated. ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated. sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag receive first byte of address 12345 789 d7 d6 d5 d4 d3 d1 ack d2 6 transmitting data byte d0 dummy read of sspbuf to clear bf flag sr cleared in software write of sspbuf initiates transmit cleared in software transmit is complete ckp has to be set for clock to be released bus master terminates transfer
pic16c717/770/771 ds41120a-page 82 advanced information ? 1999 microchip technology inc. figure 9-12: i 2 c slave-receiver (10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 2345 7 89 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 d7d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software bus master terminates transfer d2 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated with low byte of address. ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack r/w = 1 cleared in software dummy read of sspbuf to clear bf flag read of sspbuf clears bf flag cleared by hardware when sspadd is updated with high byte of address.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 83 9.2.2 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually deter- mines which device will be the slave addressed by the master. the exception is the general call address, which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all 0s with r/w = 0 the general call address is recognized when the gen- eral call enable bit (gcen) is enabled (sspcon2<7> is set). following a start-bit detect, 8 bits are shifted into sspsr and the address is compared against sspadd. it is also compared to the general call address, fixed in hardware. if the general call address matches, the sspsr is transferred to the sspbuf, the bf flag is set (eighth bit), and on the falling edge of the ninth bit (ack bit), the sspif flag is set. when the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the sspbuf to determine if the address was device spe- cific or a general call address. in 10-bit mode, the sspadd is required to be updated for the second half of the address to match, and the ua bit is set (sspstat<1>). if the general call address is sampled when gcen is set while the slave is config- ured in 10-bit address mode, then the second half of the address is not necessary, the ua bit will not be set, and the slave will begin receiving data after the acknowledge ( figure 9-13 ). figure 9-13: slave mode general call address sequence (7 or 10-bit mode) sda scl s sspif bf sspov cleared in software sspbuf is read r/w = 0 ack general call address address is compared to general call address gcen receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack, set interrupt flag '0' '1' (sspstat<0>) (sspcon<6>) (sspcon2<7>)
pic16c717/770/771 ds41120a-page 84 advanced information ? 1999 microchip technology inc. 9.2.3 sleep operation while in sleep mode, the i 2 c module can receive addresses or data, and when an address match or complete byte transfer occurs, wake the processor from sleep (if the ssp interrupt bit is enabled). 9.2.4 effects of a reset a reset disables the mssp module and terminates the current transfer. 9.2.5 master mode master mode operation is supported by interrupt gen- eration on the detection of the start and stop con- ditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle with both the s and p bits clear. in master mode, the scl and sda lines are manipu- lated by the mssp hardware. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): ? start condition ? stop condition ? data transfer byte transmitted/received ? acknowledge transmit ? repeated start figure 9-14: mssp block diagram (i 2 c master mode) read write sspsr start bit, stop bit, start bit detect, sspbuf internal data bus set/reset, s, p, wcol (sspstat) shift clock msb lsb sda acknowledge generate stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif reset ackstat, pen (sspcon2) rate generator sspm<3:0>,
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 85 9.2.6 multi-master operation in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when bit p (sspstat<4>) is set, or the bus is idle with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will gener- ate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored for arbitration to see if the signal level is the expected output level. this check is performed in hard- ware, with the result placed in the bclif bit. the states where arbitration can be lost are: ? address transfer ? data transfer ? a start condition ? a repeated start condition ? an acknowledge condition 9.2.7 i 2 c master operation support master mode is enabled by setting and clearing the appropriate sspm bits in sspcon and by setting the sspen bit. once master mode is enabled, the user has six options. - assert a start condition on sda and scl. - assert a repeated start condition on sda and scl. - write to the sspbuf register initiating trans- mission of data/address. - generate a stop condition on sda and scl. - configure the i 2 c port to receive data. - generate an acknowledge condition at the end of a received byte of data. 9.2.7.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a trans- fer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic '0'. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the r/w bit. in this case the r/w bit will be logic '1'. thus the first byte transmitted is a 7-bit slave address followed by a '1' to indicate receive bit. serial data is received via sda while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and end of transmission. the baud rate generator used for spi mode operation is now used to set the scl clock frequency for either 100 khz, 400 khz, or 1 mhz i 2 c operation. the baud rate generator reload value is contained in the lower 7 bits of the sspadd register. the baud rate generator will automatically begin counting on a write to the ssp- buf. once the given operation is complete (i.e. trans- mission of the last data bit is followed by ack), the internal clock will automatically stop counting and the scl pin will remain in its last state a typical transmit sequence would go as follows: a) the user generates a start condition by setting the start enable bit (sen) in sspcon2. b) sspif is set. the module will wait the required start time before any other operation takes place. c) the user loads the sspbuf with address to transmit. d) address is shifted out the sda pin until all 8 bits are transmitted. e) the mssp module shifts in the ack bit from the slave device, and writes its value into the sspcon2 register ( sspcon2<6>). f) the module generates an interrupt at the end of the ninth clock cycle by setting sspif. g) the user loads the sspbuf with eight bits of data. h) data is shifted out the sda pin until all 8 bits are transmitted. note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to initiate transmission before the start condition is complete. in this case, the sspbuf will not be written to, and the wcol bit will be set, indicating that a write to the sspbuf did not occur.
pic16c717/770/771 ds41120a-page 86 advanced information ? 1999 microchip technology inc. i) the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register ( sspcon2<6>). j) the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. k) the user generates a stop condition by setting the stop enable bit pen in sspcon2. l) interrupt is generated once the stop condition is complete. 9.2.8 baud rate generator in i 2 c master mode, the reload value for the brg is located in the lower 7 bits of the sspadd register ( figure 9-15 ). when the brg is loaded with this value, the brg counts down to 0 and stops until another reload has taken place. the brg count is decremented twice per instruction cycle (t cy ) on the q2 and q4 clock. in i 2 c master mode, the brg is reloaded automatically. if clock arbitration is taking place for instance, the brg will be reloaded when the scl pin is sampled high ( figure 9-16 ). figure 9-15: baud rate generator block diagram figure 9-16: baud rate generator timing with clock arbitration sspm<3:0> brg down counter clkout f osc /4 sspadd<6:0> sspm<3:0> scl reload control reload sda scl scl de-asserted but slave holds dx-1 dx brg scl is sampled high, reload takes place, and brg starts its count. 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements (on q2 and q4 cycles)
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 87 9.2.9 i 2 c master mode start condition timing to initiate a start condition, the user sets the start condition enable bit, sen (sspcon2<0>). if the sda and scl pins are sampled high, the baud rate genera- tor is re-loaded with the contents of sspadd<6:0>, and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition, and causes the s bit (sspstat<3>) to be set. follow- ing this, the baud rate generator is reloaded with the contents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspcon2<0>) will be automatically cleared by hardware, the baud rate generator is suspended leaving the sda line held low, and the start condition is complete. 9.2.9.1 wcol status flag if the user writes the sspbuf when an start sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). figure 9-17: first start bit timing note: if at the beginning of start condition, the sda and scl pins are already sampled low, or if during the start condition, the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag (bclif) is set, the start condition is aborted, and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. sda scl s t brg 1st bit 2nd bit t brg sda = 1, at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here. set s bit (sspstat<3>) and sets sspif bit
pic16c717/770/771 ds41120a-page 88 advanced information ? 1999 microchip technology inc. figure 9-18: start condition flowchart idle mode sen (sspcon2<0> = 1 ) bus collision detected, set bclif, sda = 1? load brg with ye s brg rollover? force sda = 0, load brg with sspadd<6:0>, no ye s force scl = 0, clear sen set s bit. sspadd<6:0> scl = 1? sda = 0? no ye s brg rollover? no clear sen start condition done, no ye s reset brg scl= 0? no ye s scl = 0? no ye s reset brg release scl, sspen = 1, sspcon<3:0> = 1000 and set sspif
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 89 9.2.10 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspcon2<1>) is set high and the i 2 c module is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded with the contents of sspadd<6:0>, and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sda is sampled high, the scl pin will be de-asserted (brought high). when scl is sampled high the baud rate generator is re-loaded with the contents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda is low) for one t brg while scl is high. following this, the rsen bit in the sspcon2 register will be automatically cleared, and the baud rate generator is not reloaded, leaving the sda pin held low. as soon as a start con- dition is detected on the sda and scl pins, the s bit (sspstat<3>) will be set. the sspif bit will not be set until the baud rate generator has timed-out. immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. after the first eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 9.2.10.1 wcol status flag if the user writes the sspbuf when a repeated start sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). figure 9-19: repeat start condition waveform note 1: if rsen is set while any other event is in progress, it will not take effect. note 2: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low to high. ? scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data "1". note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the repeated start condition is complete. sda scl sr = repeated start write to sspcon2 write to sspbuf occurs here. falling edge of ninth clock end of xmit at completion of start bit, hardware clear rsen bit 1st bit set s (sspstat<3>) t brg t brg sda = 1, sda = 1, scl (no change) scl = 1 occurs here. t brg t brg t brg and set sspif
pic16c717/770/771 ds41120a-page 90 advanced information ? 1999 microchip technology inc. figure 9-20: repeated start condition flowchart (page 1) idle mode, sspen = 1, force scl = 0 scl = 0? release sda, load brg with scl = 1? no ye s no ye s brg no ye s release scl sspcon<3:0> = 1000 rollover? sspadd<6:0> load brg with sspadd<6:0> (clock arbitration) a b c sda = 1? no ye s start rsen = 1 bus collision, set bclif, release sda, clear rsen
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 91 figure 9-21: repeated start condition flowchart (page 2) force sda = 0, load brg with sspadd<6:0> ye s repeated start clear rsen, ye s brg rollover? brg rollover? ye s sda = 0? no scl = 1? no b set s c a no no ye s force scl = 0, reset brg set sspif. scl = '0'? reset brg no ye s condition done,
pic16c717/770/771 ds41120a-page 92 advanced information ? 1999 microchip technology inc. 9.2.11 i 2 c master mode transmission transmission of a data byte, a 7-bit address, or either half of a 10-bit address is accomplished by simply writ- ing a value to the sspbuf register. this action will set the buffer full flag (bf) and allow the baud rate genera- tor to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time spec). scl is held low for one baud rate generator roll over count (t brg ). data should be valid before scl is released high (see data setup time spec). when the scl pin is released high, it is held that way for t brg , the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda allowing the slave device being addressed to respond with an ack bit during the ninth bit time, if an address match occurs or if data was received properly. the status of ack is read into the ackdt on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit (ackstat) is cleared. if not, the bit is set. after the ninth clock the sspif is set, and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf leav- ing scl low and sda unchanged ( figure 9-23 ). after the write to the sspbuf, each bit of address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the fall- ing edge of the eighth clock, the master will de-assert the sda pin allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit (sspcon2<6>). following the falling edge of the ninth clock transmis- sion of the address, the sspif is set, the bf flag is cleared, and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to float. 9.2.11.1 bf status flag in transmit mode, the bf bit (sspstat<0>) is set when the cpu writes to sspbuf and is cleared when all 8 bits are shifted out. 9.2.11.2 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e. sspsr is still shifting out a data byte), then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). wcol must be cleared in software. 9.2.11.3 ackstat status flag in transmit mode, the ackstat bit (sspcon2<6>) is cleared when the slave has sent an acknowledge (ack = 0), and is set when the slave does not acknowl- edge (ack = 1). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 93 figure 9-22: master transmit flowchart idle mode num_clocks = 0, release sda so slave can drive ack, num_clocks load brg with sda = current data bit ye s brg rollover? no brg no ye s force scl = 0 = 8? ye s no ye s brg rollover? no force scl = 1, stop brg scl = 1? load brg with count high time rollover? no read sda and place into ackstat bit (sspcon2<6>) force scl = 0, scl = 1? sda = data bit? no ye s ye s rollover? no ye s stop brg, force scl = 1 (clock arbitration) (clock arbitration) num_clocks = num_clocks + 1 bus collision detected set bclif, hold prescale off, ye s no bf = 1 force bf = 0 sspadd<6:0>, start brg count, load brg with sspadd<6:0>, start brg count sspadd<6:0>, load brg with count scl high time sspadd<6:0>, sda = data bit? ye s no clear xmit enable scl = 0? no ye s reset brg write sspbuf set sspif
pic16c717/770/771 ds41120a-page 94 advanced information ? 1999 microchip technology inc. figure 9-23: i 2 c master mode timing (transmission, 7 or 10-bit address) sda scl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from ssp interrupt after start condition sen cleared by hardware. s sspbuf written with 7 bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 start condition begins from slave clear ackstat bit sspcon2<6> ackstat in sspcon2 = 1 cleared in software sspbuf written pen cleared in software r/w
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 95 9.2.12 i 2 c master mode reception master mode reception is enabled by setting the receive enable bit, rcen (sspcon2<3>). the baud rate generator begins counting, and on each rollover, the state of the scl pin changes (high to low/ low to high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf flag is set, the sspif is set, and the baud rate generator is sus- pended from counting, holding scl low. the ssp is now in idle state, awaiting the next command. when the buffer is read by the cpu, the bf flag is automati- cally cleared. the user can then send an acknowledge bit at the end of reception, by setting the acknowledge sequence enable bit, acken (sspcon2<4>). 9.2.12.1 bf status flag in receive operation, bf is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when sspbuf is read. 9.2.12.2 sspov status flag in receive operation, sspov is set when 8 bits are received into the sspsr, and the bf flag is already set from a previous reception. 9.2.12.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e. sspsr is still shifting in a data byte), then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). note: the mssp module must be in an idle state before the rcen bit is set, or the rcen bit will be disregarded.
pic16c717/770/771 ds41120a-page 96 advanced information ? 1999 microchip technology inc. figure 9-24: master receiver flowchart idle mode num_clocks = 0, release sda force scl=0, ye s no brg rollover? release scl ye s no scl = 1? load brg with ye s no brg rollover? (clock arbitration) load brg w/ start count sspadd<6:0>, start count. sample sda, shift data into sspsr num_clocks = num_clocks + 1 ye s num_clocks = 8? no force scl = 0, set sspif, set bf. move contents of sspsr into sspbuf, clear rcen. rcen = 1 sspadd<6:0>, scl = 0? ye s no
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 97 figure 9-25: i 2 c master mode timing (reception 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 1 transmit address to slave sspif bf ack is not sent write to sspcon2<0>, (sen = 1) write to sspbuf occurs here ack from slave master configured as a receiver by programming sspcon2<3>, (rcen = 1) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sda = 0, scl = 1 while cpu (sspstat<0>) ack last bit is shifted into sspsr and contents are unloaded into sspbuf cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken start acknowledge sequence sspov is set because sspbuf is still full sda = ackdt = 1 rcen cleared automatically rcen = 1 start next receive write to sspcon2<4> to start acknowledge sequence sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition cleared in software sda = ackdt = 0
pic16c717/770/771 ds41120a-page 98 advanced information ? 1999 microchip technology inc. 9.2.13 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspcon2<4>). when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit is presented on the sda pin. if the user wishes to generate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ), and the scl pin is de-asserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off, and the mssp module then goes into idle mode. ( figure 9-26 ) 9.2.13.1 wcol status flag if the user writes the sspbuf when an acknowledged sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). figure 9-26: acknowledge sequence waveform note: t brg = one baud rate generator period. sda scl set sspif at the end acknowledge sequence starts here, write to sspcon2 acken automatically cleared cleared in t brg t brg of receive ack 8 acken = 1, ackdt = 0 d0 9 sspif software set sspif at the end of acknowledge sequence cleared in software
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 99 figure 9-27: acknowledge flowchart idle mode force scl = 0 ye s no scl = 0? drive ackdt bit ye s no brg rollover? (sspcon2<5>) onto sda pin, load brg with sspadd<6:0>, start count. force scl = 1 ye s no scl = 1? no ackdt = 1? load brg with no brg rollover? sspadd <6:0>, start count. no sda = 1? bus collision detected, set bclif, ye s force scl = 0, (clock arbitration) clear acken no scl = 0? reset brg clear acken, set acken release scl, ye s ye s ye s set sspif
pic16c717/770/771 ds41120a-page 100 advanced information ? 1999 microchip technology inc. 9.2.14 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit pen (sspcon2<2>). at the end of a receive/trans- mit, the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low . when the sda line is sam- pled low, the baud rate generator is reloaded and counts down to 0. when the baud rate generator times out, the scl pin will be brought high and one t brg (baud rate generator rollover count) later, the sda pin will be de-asserted. when the sda pin is sampled high while scl is high, the p bit (sspstat<4>) is set. a t brg later the pen bit is cleared and the sspif bit is set ( figure 9-28 ). whenever the firmware decides to take control of the bus, it will first determine if the bus is busy by checking the s and p bits in the sspstat register. if the bus is busy, then the cpu can be interrupted (notified) when a stop bit is detected (i.e. bus is free). 9.2.14.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). figure 9-28: stop condition receive or transmit mode scl sda sda asserted low before rising edge of clock write to sspcon2 set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat<4>) is set t brg to setup stop condition. ack p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 101 figure 9-29: stop condition flowchart idle mode, sspen = 1, force sda = 0 scl doesnt change sda = 0? de-assert scl, scl = 1 scl = 1? no ye s start brg no ye s brg sda going from 0 to 1 while scl = 1 no ye s set sspif, release sda, start brg stop condition done sspcon<3:0> = 1000 rollover? no brg rollover? ye s p bit set? no ye s bus collision detected, set bclif, clear pen start brg no ye s brg rollover? (clock arbitration) pen = 1 pen cleared.
pic16c717/770/771 ds41120a-page 102 advanced information ? 1999 microchip technology inc. 9.2.15 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, de- asserts the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate gen- erator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sam- pled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device ( figure 9-30 ). 9.2.16 sleep operation while in sleep mode, the i 2 c module can receive addresses or data, and when an address match or complete byte transfer occurs, wake the processor from sleep ( if the ssp interrupt is enabled). 9.2.17 effects of a reset a reset disables the mssp module and terminates the current transfer. figure 9-30: clock arbitration timing in master transmit mode scl sda brg overflow, release scl, if scl = 1 load brg with sspadd<6:0>, and start count brg overflow occurs, release scl, slave device holds scl low. scl = 1 brg starts counting clock high interval. scl line sampled once every machine cycle (t osc 4). hold off brg until scl is sampled high. t brg t brg t brg to measure high time interval
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 103 9.2.18 multi -master communication, bus collision, and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a '1' on sda by letting sda float high and another master asserts a '0'. when the scl pin floats high, data should be stable. if the expected data on sda is a '1' and the data sampled on the sda pin = '0', then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif, and reset the i 2 c port to its idle state. ( figure 9-31 ). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are de-asserted, and the sspbuf can be written to. when the user services the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are de-asserted, and the respective control bits in the sspcon2 register are cleared. when the user services the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communica- tion by asserting a start condition. the master will continue to monitor the sda and scl pins, and if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit, regardless of where the trans- mitter left off when bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat reg- ister, or the bus is idle and the s and p bits are cleared. figure 9-31: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high data doesnt match what is driven bus collision has occurred. set bus collision interrupt. by the master. by master data changes while scl = 0
pic16c717/770/771 ds41120a-page 104 advanced information ? 1999 microchip technology inc. 9.2.18.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition ( figure 9-32 ). b) scl is sampled low before sda is asserted low. ( figure 9-33 ). during a start condition both the sda and the scl pins are monitored. if: the sda pin is already low or the scl pin is already low, then: the start condition is aborted, and the bclif flag is set, and the ssp module is reset to its idle state ( figure 9-32 ). the start condition begins with the sda and scl pins de-asserted. when the sda pin is sampled high, the baud rate generator is loaded from sspadd<6:0> and counts down to 0. if the scl pin is sampled low while sda is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early ( figure 9-34 ). if however a '1' is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to 0, and during this time, if the scl pins is sampled as '0', a bus collision does not occur. at the end of the brg count the scl pin is asserted low. figure 9-32: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision, because the two masters must be allowed to arbitrate the first address follow- ing the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1, scl=1 sda = 0, scl = 1 bclif s sspif sda = 0, scl = 1 sspif and bclif are cleared in software. sspif and bclif are cleared in software. set bclif, set bclif. start condition.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 105 figure 9-33: bus collision during start condition (scl = 0) figure 9-34: brg reset due to sda collision during start condition sda scl sen bus collision occurs, set bclif. scl = 0 before sda = 0, set sen, enable start sequence if sda = 1, scl = 1 t brg t brg sda = 0, scl = 1 bclif s sspif interrupts cleared in software. bus collision occurs, set bclif. scl = 0 before brg time out, '0' '0' '0' '0' sda scl sen set s set sen, enable start sequence if sda = 1, scl = 1 less than t brg t brg sda = 0, scl = 1 bclif s sspif s interrupts cleared in software. set sspif sda = 0, scl = 1 sda pulled low by other master. reset brg and assert sda scl pulled low after brg timeout set sspif '0'
pic16c717/770/771 ds41120a-page 106 advanced information ? 1999 microchip technology inc. 9.2.18.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indi- cating that another master is attempting to trans- mit a data 1. when the user de-asserts sda and the pin is allowed to float high, the brg is loaded with sspadd<6:0>, and counts down to 0. the scl pin is then de- asserted, and when sampled high, the sda pin is sam- pled. if sda is low, a bus collision has occurred (i.e. another master is attempting to transmit a data 0). if however sda is sampled high, then the brg is reloaded and begins counting. if sda goes from high to low before the brg times out, no bus collision occurs, because no two masters can assert sda at exactly the same time. if, however, scl goes from high to low before the brg times out and sda has not already been asserted, then a bus collision occurs. in this case, another master is attempting to transmit a data 1 during the repeated start condition. if at the end of the brg time out both scl and sda are still high, the sda pin is driven low, the brg is reloaded, and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is com- plete ( figure 9-35 ). figure 9-35: bus collision during a repeated start condition (case 1) figure 9-36: bus collision during repeated start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0, set bclif and release sda and scl cleared in software '0' '0' '0' '0' sda scl bclif rsen s sspif interrupt cleared in software scl goes low before sda, set bclif. release sda and scl t brg t brg '0' '0' '0' '0'
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 107 9.2.18.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been de-asserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is de-asserted, scl is sam- pled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allow to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd<6:0> and counts down to 0. after the brg times out sda is sam- pled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data '0'. if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data '0' ( figure 9-37 ). figure 9-37: bus collision during a stop condition (case 1) figure 9-38: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif '0' '0' '0' '0' sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high set bclif '0' '0'
pic16c717/770/771 ds41120a-page 108 advanced information ? 1999 microchip technology inc. 9.2.19 connection considerations for i 2 c bus for standard-mode i 2 c bus devices, the values of resistors r p and r s in figure 9-39 depends on the fol- lowing parameters ? supply voltage ? bus capacitance ? number of connected devices (input current + leakage current). the supply voltage limits the minimum value of resistor r p due to the specified minimum sink current of 3 ma at v ol max = 0.4v for the specified output stages. for example, with a supply voltage of v dd = 5v+ 10% and v ol max = 0.4v at 3 ma, r p min = (5.5-0.4)/0.003 = 1.7 k w. v dd as a function of r p is shown in figure 9-39. the desired noise margin of 0.1v dd for the low level limits the maximum value of r s . series resistors are optional and used to improve esd susceptibility. the bus capacitance is the total capacitance of wire, connections, and pins. this capacitance limits the max- imum value of r p due to the specified rise time ( figure 9-39 ). the smp bit is the slew rate control enabled bit. this bit is in the sspstat register, and controls the slew rate of the i/o pins when in i 2 c mode (master or slave). figure 9-39: sample device configuration for i 2 c bus table 9-3: registers associated with i 2 c operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 por, bor mclr , wdt 0bh, 8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 0dh pir2 lv d i f bclif ccp2if 0--- 0--0 0--- 0--0 8dh pie2 lvd i e bclie ccp2ie 0--- 0--0 0--- 0--0 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 91h sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 94h sspstat smp cke d/a psr/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the mssp in i 2 c mode. r p r p v dd + 10% sda scl note: i 2 c devices with input levels related to v dd must have one common supply line to which the pull-up resistor is also connected. device c b =10 pf to 400 pf r s r s
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 109 10.0 voltage reference module and low-voltage detect the voltage reference module provides reference volt- ages for the brown-out reset circuitry, the low-voltage detect circuitry and the a/d converter. the source for the reference voltages comes from the bandgap reference circuit. the bandgap circuit is ener- gized anytime the reference voltage is required by the other sub-modules, and is powered down when not in use. the control registers for this module are lvdcon and refcon, as shown in register 10-1 and figure 10-2. register 10-1: low-voltage detect control register (lvdcon: 9ch) u-0 u-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 bgst lvden lv3 lv2 lv1 lv0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5: bgst: bandgap stable status flag bit 1 = indicates that the bandgap voltage is stable, and lvd interrupt is reliable 0 = indicates that the bandgap voltage is not stable, and lvd interrupt should not be enabled bit 4: lvden: low-voltage detect power enable bit 1 = enables lvd, powers up bandgap circuit and reference generator 0 = disables lvd, powers down bandgap circuit if unused by bor or vrh/vrl bit 3-0: lv<3:0>: low voltage detection limit bits (1) 1111 = external analog input is used 1110 = 4.5v 1101 = 4.2v 1100 = 4.0v 1011 = 3.8v 1010 = 3.6v 1001 = 3.5v 1000 = 3.3v 0111 = 3.0v 0110 = 2.8v 0101 = 2.7v 0100 = 2.5v 0011 = reserved. do not use. 0010 = reserved. do not use. 0001 = reserved. do not use. 0000 = reserved. do not use. note 1: these are the minimum trip points for the lvd. see table 15-3 for the trip point tolerances. selection of reserved setting may result in an inadvertent interrupt.
pic16c717/770/771 ds41120a-page 110 advanced information ? 1999 microchip technology inc. register 10-2: voltage reference control register (refcon: 9bh) 10.1 bandgap voltage reference the bandgap module generates a stable voltage refer- ence of over a range of temperatures and device supply voltages. this module is enabled anytime any of the fol- lowing are enabled: ? brown-out reset ? low-voltage detect ? either of the internal analog references (vrh, vrl) whenever the above are all disabled, the bandgap module is disabled and draws no current. 10.2 internal v ref for a/d converter the bandgap output voltage is used to generate two stable references for the a/d converter module. these references are enabled in software to provide the user with the means to turn them on and off in order to min- imize current consumption. each reference can be indi- vidually enabled. the vrh reference is enabled with control bit vrhen (refcon<7>). when this bit is set, the gain amplifier is enabled. after a specified start-up time a stable ref- erence of 4.096v nominal is generated and can be used by the a/d converter as a reference input. the vrl reference is enabled by setting control bit vrlen (refcon<6>). when this bit is set, the gain amplifier is enabled. after a specified start up time a stable reference of 2.048v nominal is generated and can be used by the a/d converter as a reference input. each voltage reference is available for external use via vrl and vrh pins. each reference, if enabled, can be output on an exter- nal pin by setting the vrhoen (high reference output enable) or vrloen (low reference output enable) con- trol bit. if the reference is not enabled, the vrhoen and vrloen bits will have no effect on the corre- sponding pin. the device specific pin can then be used as general purpose i/o. r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 vrhen vrlen vrhoen vrloen r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: vrhen: voltage reference high enable bit (vrh = 4.096v nominal) 1 = enabled, powers up reference generator 0 = disabled, powers down reference generator if unused by lvd, bor, or vrl bit 6: vrlen: voltage reference low enable bit (vrl = 2.048v nominal) 1 = enabled, powers up reference generator 0 = disabled, powers down reference generator if unused by lvd, bor, or vrh bit 5: vrhoen: high voltage reference output enable bit 1 = enabled, vrh analog reference is output on ra3 if enabled (vrhen = 1) 0 = disabled, analog reference is used internally only bit 4: vrloen: low voltage reference output enable bit 1 = enabled, vrl analog reference is output on ra2 if enabled (vrlen = 1) 0 = disabled, analog reference is used internally only bit 3-0: unimplemented: read as '0 note: if vrh or vrl is enabled and the other ref- erence (vrl or vrh), the bor, and the lvd modules are not enabled, the band- gap will require a start-up time before the bandgap reference is stable. before using the internal vrh or vrl reference, ensure that the bandgap reference voltage is sta- ble by monitoring the bgst bit in the lvd- con register. the voltage references will not be reliable until the bandgap is stable as shown by bgst being set.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 111 10.3 low-voltage detect (lvd) this module is used to generate an interrupt when the supply voltage falls below a specified trip voltage. this module operates completely under software control. this allows a user to power the module on and off to periodically monitor the supply voltage, and thus minimize total current consumption. figure 10-1: block diagram of lvd and voltage reference circuit the lvd module is enabled by setting the lvden bit in the lvdcon register. the trip point voltage is the minimum supply voltage level at which the device can operate before the lvd module asserts an interrupt. when the supply voltage is equal to or less than the trip point, the module will generate an interrupt signal set- ting interrupt flag bit lvdif. if interrupt enable bit lvdie was set, then an interrupt is generated. the lvd inter- rupt can wake the device from sleep. the "trip point" voltage is software programmable to any one of 16 val- ues, five of which are reserved (see figure 10-1). the trip point is selected by programming the lv<3:0> bits (lvdcon<3:0>). once the lv bits have been programmed for the speci- fied trip voltage, the low-voltage detect circuitry is then enabled by setting the lvden (lvdcon<4>) bit. if the bandgap reference voltage is previously unused by either the brown-out circuitry or the voltage refer- ence circuitry, then the bandgap circuit requires a time to start-up and become stable before a low voltage con- dition can be reliably detected. the low-voltage inter- rupt flag is prevented from being set until the bandgap has reached a stable reference voltage. when the bandgap is stable the bgst (lvdcon<5>) bit is set indicating that the low-voltage interrupt flag bit is released to be set if v dd is equal to or less than the lvd trip point. 10.3.1 external analog voltage input the lvd module has an additional feature that allows the user to supply the trip voltage to the module from an external source. this mode is enabled when lv<3:0> = 1111 . when these bits are set the compar- ator input is multiplexed from an external input pin (ra1/an1/lvdin). v dd generates 16 to 1 mux bgap vrh vrl lv d e n lv d c o n refcon boden lv d e n vrhen + vrlen ra1/an1/lvdin lv d i f note: the lvdif bit can not be cleared until the supply voltage rises above the lvd trip point. if interrupts are enabled, clear the lvdie bit once the first lvd interrupt occurs to prevent reentering the interrupt service routine immediately after exiting the isr.
pic16c717/770/771 ds41120a-page 112 advanced information ? 1999 microchip technology inc. notes:
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 113 11.0 analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has six inputs for the pic16c717/770/771. the pic16c717 analog-to-digital converter (a/d) allows conversion of an analog input signal to a corre- sponding 10-bit digital value, while the a/d converter in the pic16c770/771 allows conversion to a corre- sponding 12-bit digital value. the a/d module has up to 6 analog inputs, which are multiplexed into one sample and hold. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. the analog reference voltages are software selectable to either the devices analog positive and negative supply voltages (av dd / av ss ), the voltage level on the v ref + and v ref - pins, or internal voltage references if enabled (vrh, vrl). the a/d converter can be triggered by setting the go/ done bit, or by the special event compare mode of the eccp1 module. when conversion is complete, the go/done bit returns to 0, the adif bit in the pir1 register is set, and an a/d interrupt will occur, if enabled. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to operate in sleep, the a/d conversion clock must be derived from the a/ds internal rc oscillator. the a/d module has four registers. these registers are: ? a/d result register low adresl ? a/d result register high adresh ? a/d control register 0 (adcon0) ? a/d control register 1 (adcon1) a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion is aborted. 11.1 control registers the adcon0 register, shown in register 11-1 , con- trols the operation of the a/d module. the adcon1 register, shown in register 11-2 , configures the func- tions of the port pins, the voltage reference configura- tion and the result format. the port pins can be configured as analog inputs or as digital i/o. the combination of the adresh and adresl regis- ters contain the result of the a/d conversion. the reg- ister pair is referred to as the adres register. when the a/d conversion is complete, the result is loaded into adres, the go/done bit (adcon0<2>) is cleared, and the a/d interrupt flag adif is set. the block diagram of the a/d module is shown in figure 11-3 .
pic16c717/770/771 ds41120a-page 114 advanced information ? 1999 microchip technology inc. register 11-1: a/d control register 0 (adcon0: 1fh). r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done chs3 adon r = readable bit w = writable bit - n = value at por reset bit7 bit 0 bit 7-6: adcs<1:0>: a/d conversion clock select bits if internal vrl and/or vrh are not used for a/d reference (vcfg<2:0> = 000, 001, 011 or 101 ): 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (clock derived from a dedicated rc oscillator = 1 mhz max) if internal vrl and/or vrh are used for a/d reference (vcfg<2:0> = 010, 100, 110 or 111 ): 00 = f osc /16 01 = f osc /64 10 = f osc /256 11 = f rc (clock derived from a dedicated rc oscillator = 125 khz max) bit 1,5-3: chs:<3:0>: analog channel select bits 0000 = channel 00 (an0) 0001 = channel 01 (an1) 0010 = channel 02 (an2) 0011 = channel 03 (an3) 0100 = channel 04 (an4) 0101 = channel 05 (an5) 0110 = reserved, do not select 0111 = reserved, do not select 1000 = reserved, do not select 1001 = reserved, do not select 1010 = reserved, do not select 1011 = reserved, do not select 1100 = reserved, do not select 1101 = reserved, do not select 1110 = reserved, do not select 1111 = reserved, do not select bit 2: go/done : a/d conversion status bit 1 = a/d conversion cycle in progress. setting this bit starts an a/d conversion cycle. this bit is automatically cleared by hardware when the a/d conversion has completed. 0 = a/d conversion completed/not in progress bit 0: adon: a/d on bit 1 = a/d converter module is operating 0 = a/d converter is shutoff and consumes no operating current
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 115 register 11-2: a/d control register 1 (adcon1: 9fh) the value that is in the adresh and adresl regis- ters are not modified for a power-on reset. the adresh and adresl registers will contain unknown data after a power-on reset. the a/d conversion results can be left justified (adfm bit cleared), or right justified (adfm bit set). figure 11-1 through figure 11-2 show the a/d result data format of the pic16c717/770/771. figure 11-1: pic16c770/771 12-bit a/d result formats r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm vcfg2 vcfg1 vcfg0 reserved r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit 0 bit 7: adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6-4: vcfg<2:0>: voltage reference configuration bits bit 3-0: reserved: do not use. a/d v ref + a/d v ref - 000 av dd av ss 001 external v ref + external v ref - 010 internal vrh internal vrl 011 external v ref +av ss 100 internal vrh av ss 101 av dd external v ref - 110 av dd internal vrl 111 internal vrl av ss adresh (1eh) adresl (9eh) left justified (adfm = 0) msb lsb bit7 bit7 12-bit a/d result unused right justified (adfm = 1) msb lsb bit7 bit7 unused 12-bit a/d result
pic16c717/770/771 ds41120a-page 116 advanced information ? 1999 microchip technology inc. figure 11-2: pic16c717 10-bit a/d result format after the a/d module has been configured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris and ansel bits selected as an input. to determine acquisition time, see section 11.6 . after this acquisition time has elapsed, the a/d conversion can be started. the following steps should be followed for doing an a/d conversion: 11.2 configuring the a/d module 11.2.1 configuring analog port pins the ansel and tris registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bit set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the proper ansel bits must be set (analog input) to disable the digital input buffer. the a/d operation is independent of the state of the tris bits and the ansel bits. 11.2.2 configuring the reference voltages the vcfg bits in the adcon1 register configure the a/d module reference inputs. the reference high input can come from an internal reference (vrh) or (vrl), an external reference (v ref +), or av dd . the low reference input can come from an internal refer- ence (vrl), an external reference (v ref -), or av ss . if an external reference is chosen for the reference high or reference low inputs, the port pin that multiplexes the incoming external references is configured as an analog input, regardless of the values contained in the a/d port configuration bits (pcfg<3:0>). (adfm = 0) msb lsb bit7 bit7 10-bit a/d result unused (adfm = 1) msb lsb bit7 bit7 unused 10-bit a/d result unused note 1: when reading the porta or portb reg- ister, all pins configured as analog input channels will read as 0. 2: analog levels on any pin that is defined as a digital input, including the anx pins, may cause the input buffer to consume current that is out of the devices specification.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 117 after the a/d module has been configured as desired and the analog input channels have their correspond- ing tris bits selected for port inputs, the selected channel must be acquired before conversion is started. the a/d conversion cycle can be initiated by setting the go/done bit. the a/d conversion begins and lasts for 13t ad . the following steps should be fol- lowed for performing an a/d conversion: 1. configure port pins: ? configure analog input mode (ansel) ? configure pin as input (trisa or trisb) 2. configure the a/d module ? configure a/d result format / voltage refer- ence (adcon1) ? select a/d input channel (adcon0) ? select a/d conversion clock (adcon0) ? turn on a/d module (adcon0) 3. configure a/d interrupt (if required) ? clear adif bit ? set adie bit ? set peie bit ? set gie bit 4. wait the required acquisition time (3t ad ) 5. start conversion ? set go/done bit (adcon0) 6. wait 13t ad until a/d conversion is complete, by either: ? polling for the go/done bit to be cleared or ? waiting for the a/d interrupt 7. read a/d result registers (adresh and adresl), clear adif if required. 8. for next conversion, go to step 1, step 2 or step 3 as required. clearing the go/done bit during a conversion will abort the current conversion. the adresh and adresl registers will be updated with the partially completed a/d conversion value. that is, the adresh and adresl registers will contain the value of the current incomplete conversion. figure 11-3: a/d block diagram note: do not set the adon bit and the go/ done bit in the same instruction. doing so will cause the go/done bit to be automat- ically cleared. (input voltage) v ain v ref + (reference voltage +) av dd vcfg<2:0> chs<3:0> rb1/an5/ss rb0/an4/int ra3/an3/v ref +/vrh ra2/an2/v ref -/vrl ra1/an1 ra0/an0 a/d converter v ref - (reference voltage -) av ss vcfg<2:0> vrh vrl vrl
pic16c717/770/771 ds41120a-page 118 advanced information ? 1999 microchip technology inc. 11.3 selecting the a/d conversion clock the a/d conversion cycle requires 13t ad : 1 t ad for set- tling time, and 12 t ad for conversion. the source of the a/d conversion clock is software selected. if neither the internal vrh nor vrl are used for the a/d converter, the four possible options for t ad are: ?2 t osc ?8 t osc ?32 t osc ? a/d rc oscillator if the vrh or vrl are used for the a/d converter refer- ence, then the t ad requirement is automatically increased by a factor of 8. for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 m s. ta bl e 1 1 - 1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. the adif bit is set on the rising edge of the 14th t ad . the go/done bit is cleared on the falling edge of the 14th t ad . table 11-1: t ad vs. device operating frequencies a/d reference source a/d clock source (t ad ) device frequency external v ref or analog supply operation adcs<1:0> 20 mhz 5 mhz 4 mhz 1.25 mhz 2 t osc 00 100 ns (2) 400 ns (2) 500 ns (2) 1.6 m s 8 t osc 01 800 ns (2) 1.6 m s2.0 m s6.4 m s 32 t osc 10 1.6 m s6.4 m s 8.0 m s (3) 24 m s (3) a/d rc 11 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) internal vrh or vrl 16 t osc 00 800 ns (2) 3.2 m s (2) 4 m s (2) 12.8 m s 64 t osc 01 6.4 m s (2) 12.8 m s 16 m s 51.2 m s 256 t osc 10 12.8 m s51.2 m s 64 m s (3) 192 m s (3) a/d rc 11 16 - 48 m s (4,5) 16 - 48 m s (4,5) 16 - 48 m s (4,5) 16 - 48 m s (4,5) legend: shaded cells are outside of recommended range. note 1: the a/d rc source has a typical t ad time of 4 m s for v dd > 3.0v. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: when the device frequency is greater than 1 mhz, the a/d rc clock source is only recommended if the conversion will be performed during sleep. 5: the resource has a typical t ad time of 32 m s for v dd > 3.0v.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 119 11.4 a/d conversions example 11-1 shows an example that performs an a/d conversion. the port pins are configured as analog inputs. the analog reference v ref + is the device av dd and the analog reference v ref - is the device av ss . the a/d interrupt is enabled and the a/d conversion clock is t rc . the conversion is performed on the an0 channel. example 11-1: performing an a/d conversion bcf pir1, adif ;clear a/d int flag bsf status, rp0 ;select bank 1 clrf adcon1 ;configure a/d voltage reference movlw 0x01 movwf ansel ;disable an0 digital input buffer movwf trisa ;ra0 is input mode bsf pie1, adie ;enable a/d interrupt bcf status, rp0 ;select bank 0 movlw 0xc1 ;rc clock, a/d is on, ;ch 0 is selected movwf adcon0 ; bsf intcon, peie ;enable peripheral bsf intcon, gie ;enable all interrupts ; ; ensure that the required sampling time for the ; selected input channel has lapsed. then the ; conversion may be started. bsf adcon0, go ;start a/d conversion : ;the adif bit will be ;set and the go/done bit : ;cleared upon completion- ;of the a/d conversion. ; wait for a/d completion and read adresh:adresl for result.
pic16c717/770/771 ds41120a-page 120 advanced information ? 1999 microchip technology inc. 11.5 a/d converter module operation figure 11-4 shows the flowchart of the a/d converter module. figure 11-4: flowchart of a/d operation sample adon = 0 adon = 0? go = 0? a/d clock go = 0 adif = 0 abort conversion sleep power down a/d wait 2 tad wake-up ye s no ye s no no ye s finish conversion go = 0 adif = 1 sleep no ye s finish conversion go = 0 adif = 1 wait 2 tad stay in sleep selected channel = rc? instruction? sleep no ye s instruction? start of a/d conversion delayed 1 instruction cycle from sleep? powerdown a/d ye s no wait 2 tad finish conversion go = 0 adif = 1
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 121 11.6 a/d sample requirements 11.6.1 recommended source impedance the maximum recommended impedance for ana- log sources is 2.5 k w . this value is calculated based on the maximum leakage current of the input pin. the leakage current is 100 na max., and the analog input voltage cannot be varied by more than 1/4 lsb or 250 m v due to leakage. this places a requirement on the input impedance of 250 m v/100 na = 2.5 k w . 11.6.2 sampling time calculation for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 11-5 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), see figure 11-5 . the maximum recom- mended impedance for analog sources is 2.5 k w . after the analog input channel is selected (changed) this sampling must be done before the conversion can be started. to calculate the minimum sampling time, equation 11- 2 may be used. this equation assumes that 1/4 lsb error is used (16384 steps for the a/d). the 1/4 lsb error is the maximum error allowed for the a/d to meet its specified resolution. the c hold is assumed to be 25 pf for the 12-bit a/d. example 11-2: a/d sampling time equation v hold =(v ref - v ref /16384) = (v ref ) ? (1 -e (-t c /c (r ic +r ss + r s ) ) v ref (1 - 1/16384) = v ref ? (1 -e (-t c /c (r ic +r ss + r s ) ) tc = -c hold (1k w + r ss + r s ) in (1/16384) figure 11-3 shows the calculation of the minimum time required to charge c hold . this calculation is based on the following system assumptions: c hold = 25 pf r s = 2.5 k w 1/4 lsb error v dd = 5v ? r ss = 10 k w (worst case) temp (system max.) = 50 c note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 2.5 k w . this is required to meet the pin leakage specifi- cation. 4: after a conversion has completed, you must wait 2 t ad time before sampling can begin again. during this time, the holding capacitor is not connected to the selected a/d input channel.
pic16c717/770/771 ds41120a-page 122 advanced information ? 1999 microchip technology inc. example 11-3: calculating the minimum required sample time t acq = amplifier settling time + holding capacitor charging time +temperature offset ? t acq =5 m s + t c + [(temp - 25 c)(0.05 m s/ c)] ? t c = holding capacitor charging time t c =(c hold ) (r ic + r ss + r s ) in (1/16384) t c = -25 pf (1 k w +10 k w + 2.5 k w ) in (1/16384) t c = -25 pf (13.5 k w ) in (1/16384) t c = -0.338 (-9.704) m s t c =3.3 m s t acq =5 m s + 3.3 m s + [(50 c - 25 c)(0.05 m s / c)] t acq =8.3 m s + 1.25 m s t acq = 9.55 m s ? the temperature coefficient is only required for temperatures > 25 c. figure 11-5: analog input model c pin va rs port pin 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic @ 1k sampling switch ss r ss c hold = 25 pf v ss 6v sampling switch (r ss ) 5v 4v 3v 2v 567891011 ( k w ) v dd 100 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 123 11.7 use of the eccp1 trigger an a/d conversion can be started by the special event trigger of the ccp module. this requires that the ccp1m<3:0> bits be programmed as 1011b and that the a/d module is enabled (adon is set). when the trigger occurs, the go/done bit will be set on q2 to start the a/d conversion and the timer1 counter will be reset to zero. timer1 is reset to automatically repeat the a/d conversion cycle, with minimal software overhead (moving the adresh and adresl to the desired location). the appropriate analog input chan- nel must be selected before the special event trigger sets the go/done bit (starts a conversion cycle). if the a/d module is not enabled (adon is cleared), then the special event trigger will be ignored by the a/d module, but will still reset the timer1 counter. 11.8 effects of a reset a device reset forces all registers to their reset state. this forces the a/d module to be turned off, and any conversion is aborted. the value that is in the adresh and adresl registers are not modified. the adresh and adresl registers will contain unknown data after a power-on reset. 11.9 faster conversion - lower resolution trade-off not all applications require a result with 12-bits of res- olution, but may instead require a faster conversion time. the a/d module allows users to make the trade- off of conversion speed to resolution. regardless of the resolution required, the acquisition time is the same. to speed up the conversion, the a/d module may be halted by clearing the go/done bit after the desired number of bits in the result have been con- verted. once the go/done bit has been cleared, all of the remaining a/d result bits are 0. the equation to determine the time before the go/done bit can be switched is as follows: conversion time = (n+1)t ad where: n = number of bits of resolution required, and 1t ad is the amplifier settling time. since t ad is based from the device oscillator, the user must use some method (a timer, software loop, etc.) to determine when the a/d go/done bit may be cleared. table 11-4 shows a comparison of time required for a conversion with 4-bits of resolution, ver- sus the normal 12-bit resolution conversion. the example is for devices operating at 20 mhz. the a/d clock is programmed for 32 t osc . example 11-4: 4-bit vs. 12-bit conversion time example 4 bit example: conversion time = (n + 1) t ad = (4 + 1) t ad = (5)(1.6 m s) = 8 m s 12 bit example: conversion time = (n + 1) t ad = (12 + 1) t ad = (13)(1.6 m s) = 20.8 m s
pic16c717/770/771 ds41120a-page 124 advanced information ? 1999 microchip technology inc. 11.10 a/d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be configured for rc (adcs<1:0> = 11b ). with the rc clock source selected, when the go/done bit is set the a/d module waits one instruction cycle before starting the conver- sion cycle. this allows the sleep instruction to be exe- cuted, which eliminates all digital switching noise during the sample and conversion. when the conver- sion cycle is completed the go/done bit is cleared, and the result loaded into the adresh and adresl registers. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d module will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction causes the present conver- sion to be aborted and the a/d module is turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. 11.11 connection considerations since the analog inputs employ esd protection, they have diodes to v dd and v ss . this requires that the analog input must be between v dd and v ss . if the input voltage exceeds this range by greater than 0.3v (either direction), one of the diodes becomes forward biased and it may damage the device if the input current spec- ification is exceeded. an external rc filter is sometimes added for anti-alias- ing of the input signal. the r component should be selected to ensure that the total source impedance is kept under the 2.5 k w recommended specification. any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. table 11-2: summary of a/d registers note: for the a/d module to operate in sleep , the a/d clock source must be configured to rc (adcs<1:0> = 11b ). address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 1eh adresh a/d high byte result register xxxx xxxx uuuu uuuu 9eh adresl a/d low byte result register xxxx xxxx uuuu uuuu 9bh refcon vrhen vrlen vrhoen vrloen 0000 ---- 0000 ---- 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done chs3 adon 0000 0000 0000 0000 9fh adcon1 adfm vcfg2 vcfg1 vcfg0 0000 ---- 0000 ---- 05h porta porta data latch when written: porta pins when read 000x 0000 000u 0000 06h portb portb data latch when written: portb pins when read xxxx xx00 uuuu uu00 85h trisa porta data direction register 1111 1111 1111 1111 86h trisb portb data direction register 1111 1111 1111 1111 9dh ansel ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used for a/d conversion.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 125 12.0 special features of the cpu these devices have a host of features intended to maximize system reliability, minimize cost through elim- ination of external components, provide power saving operating modes and offer code protection. these are: ? oscillator selection ? reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) ? interrupts ? watchdog timer (wdt) ? low-voltage detection ? sleep ? code protection ? id locations ? in-circuit serial programming (icsp) these devices have a watchdog timer, which can be shut off only through configuration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a fixed delay of 72 ms (nominal) on power-up type resets only (por, bor), designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset cir- cuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up, or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the intrc and er oscillator options save system cost while the lp crystal option saves power. a set of con- figuration bits are used to select various options. additional information on special features is available in the picmicro? mid-range reference manual, (ds33023). 12.1 configuration bits the configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. these bits are mapped in pro- gram memory location 2007h. the user will note that address 2007h is beyond the user program memory space. in fact, it belongs to the special test/configuration memory space (2000h - 3fffh), which can be accessed only during program- ming. some of the core features provided may not be neces- sary to each application that a device may be used for. the configuration word bits allow these features to be configured/enabled/disabled as necessary. these fea- tures include code protection, brown-out reset and its trippoint, the power-up timer, the watchdog timer and the devices oscillator mode. as can be seen in figure 12-1 , some additional configuration word bits have been provided for brown-out reset trippoint selec- tion.
pic16c717/770/771 ds41120a-page 126 advanced information ? 1999 microchip technology inc. figure 12-1: configuration word for 16c717/770/771 device 12.2 oscillator configurations 12.2.1 oscillator types the pic16c717/770/771 can be operated in four differ- ent oscillator modes. the user can program three con- figuration bits (fosc<2:0>) to select one of these eight modes: ? lp low power crystal ? xt crystal/resonator ? hs high speed crystal/resonator ? er external resistor (with and without clkout) ? intrc internal 4 mhz (with and without clkout) ? ec external clock 12.2.2 lp, xt and hs modes in lp, xt or hs modes, a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation ( figure 12-2 ). the pic16c717/770/771 oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers spec- ifications. cp cp borv1 borv0 cp cp boden mclre pwrte wdte fosc2 fosc1 fosc0 register: config address 2007h bit13 12 11 10 9 8 7 6 5 4 3 2 1 bit0 bit 13,12: cp : program memory code protection bit 9,8: 1 = code protection off 0 = all program memory is protected (2) bit 11-10: borv<1:0>: brown-out reset voltage bits 00 = v bor set to 4.5v 01 = v bor set to 4.2v 10 = v bor set to 2.7v 11 = v bor set to 2.5v bit 7: unimplemented: read as '1' bit 6: boden: brown-out detect reset enable bit (1) 1 = brown-out detect reset enabled 0 = brown-out detect reset disabled bit 5: mclre : ra5/mclr pin function select 1 = ra5/mclr pin function is mclr 0 = ra5/mclr pin function is digital input, mclr internally tied to v dd bit 4: pwrte : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled bit 3: wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 2-0: fosc<2:0>: oscillator selection bits 000 = lp oscillator: ceramic resonator on ra6/osc2/clkout and ra7/osc1/clkin 001 = xt oscillator: crystal on ra6/osc2/clkout and ra7/osc1/clkin 010 = hs oscillator: high frequency crystal on ra6/osc2/clkout and ra7/osc1/clkin 011 = ec: i/o function on ra6/osc2/clkout pin, clkin function on ra7/osc1/clkin 100 = intrc oscillator: i/o function on ra6/osc2/clkout pin, i/o function on ra7/osc1/clkin 101 = intrc oscillator: clkout function on ra6/osc2/clkout pin, i/o function on ra7/osc1/clkin 110 = er oscillator: i/o function on ra6/osc2/clkout pin, resistor on ra7/osc1/clkin 111 = er oscillator: clkout function on ra6/osc2/clkout pin, resistor on ra7/osc1/clkin note 1: enabling brown-out reset automatically enables the power-up timer (pwrt), regardless of the value of bit pwrte . ensure the power-up timer is enabled anytime brown-out reset is enabled. 2: all of the cp bits must be given the same value to enable code protection.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 127 figure 12-2: crystal/ceramic resonator operation (hs, xt or lp osc configuration) table 12-1: ceramic resonators table 12-2: capacitor selection for crystal oscillator 12.2.3 ec mode in applications where the clock source is external, the pic16c717/770/771 should be programmed to select the ec (external clock) mode. in this mode, the ra6/ osc2/clkout pin is available as an i/o pin. see figure 12-3 for illustration. figure 12-3: external clock input operation (ec osc configuration) ranges tested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf these values are for design guidance only. see notes at bottom of page. all resonators used did not have built-in capacitors. osc type crystal freq cap. range c1 cap. range c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf these values are for design guidance only. see notes at bottom of page. note 1: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. 2: higher capacitance increases the stability of oscillator but also increases the start-up time. note1: see ta bl e 1 2 - 1 and table 12-2 for recom- mended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen. c1(1) c2(1) xtal osc2 osc1 rf(3) sleep to logic pic16c717/770/771 rs(2) internal osc1 ra6 i/o clock from ext. system pic16c717/770/771
pic16c717/770/771 ds41120a-page 128 advanced information ? 1999 microchip technology inc. 12.2.4 er mode for timing insensitive applications, the er (external resistor) clock mode offers additional cost savings. only one external component, a resistor connected to the osc1 pin and v ss , is needed to set the operating frequency of the internal oscillator. the resistor draws a dc bias current which controls the oscillation fre- quency. in addition to the resistance value, the oscilla- tor frequency will vary from unit to unit, and as a function of supply voltage and temperature. since the controlling parameter is a dc current and not a capac- itance, the particular package type and lead frame will not have a significant effect on the resultant frequency. figure 12-4 shows how the controlling resistor is con- nected to the pic16c717/770/771. for rext values below 38k ohms, the oscillator operation may become unstable, or stop completely. for very high rext values (e.g. 1m), the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping rext between 38k and 1m ohms. figure 12-4: external resistor the electrical specification section shows the relation- ship between the rext resistance value and the operat- ing frequency as well as frequency variations due to operating temperature for given rext and v dd values. the er oscillator mode has two options that control the osc2 pin. the first allows it to be used as a general purpose i/o port. the other configures the pin as clk- out. the er oscillator does not run during reset. 12.2.5 intrc mode the internal rc oscillator provides a fixed 4 mhz (nom- inal) system clock at v dd = 5v and 25 c, see electrical specifications section for information on variation over voltage and temperature. the intrc oscillator does not run during reset. 12.2.6 clkout in the intrc and er modes, the pic16c717/770/771 can be configured to provide a clock out signal by pro- gramming the configuration word. the oscillator fre- quency, divided by 4, can be used for test purposes or to synchronize other logic. in the intrc and er modes, if the clkout output is enabled, clkout is held low during reset. 12.2.7 dual speed operation for er and intrc modes a software programmable dual speed oscillator is avail- able in either er or intrc oscillator modes. this fea- ture allows the applications to dynamically toggle the oscillator speed between normal and slow frequencies. the nominal slow frequency is 37khz. in er mode, the slow speed operation is fixed and does not vary with resistor size. applications that require low current power savings, but cannot tolerate putting the part into sleep, may use this mode. the oscf bit in the pcon register is used to control dual speed mode. see the pcon register, register 2-8 , for details. when changing the intrc or er internal oscillator speed, there is a period of time when the processor is inactive. when the speed changes from fast to slow, the processor inactive period is in the range of 100 m s to 300 m s. for speed change from slow to fast, the pro- cessor is in active for 1.25 m s to 3.25 m s. ra7/osc1/clkin ra6/osc2/clkout pic16c717/770/771 r ext
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 129 12.3 reset the pic16c717/770/771 devices have several differ- ent resets. these resets are grouped into two classifi- cations; power-up and non-power-up. the power-up type resets are the power-on and brown-out resets which assume the device v dd was below its normal operating range for the devices configuration. the non- power up type resets assume normal operating limits were maintained before/during and after the reset. ? power-on reset (por) ? programmable brown-out reset (pbor) ?mclr reset during normal operation ?mclr reset during sleep ? wdt reset (during normal operation) some registers are not affected in any reset condition. their status is unknown on a power-up reset and unchanged in any other reset. most other registers are placed into an initialized state upon reset, however they are not affected by a wdt reset during sleep, because this is considered a wdt wakeup, which is viewed as the resumption of normal operation. several status bits have been provided to indicate which reset occurred (see ta bl e 1 2 - 4 ). see ta bl e 1 2 - 6 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 12-5 . these devices have a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. figure 12-5: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt dedicated oscillator power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter enable ost enable pwrt sleep brown-out programmable boden time-out
pic16c717/770/771 ds41120a-page 130 advanced information ? 1999 microchip technology inc. 12.4 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.5v - 2.1v). to take advantage of the por, just enable the internal mclr feature. this will eliminate external rc compo- nents usually needed to create a power-on reset. a maximum rise time for v dd is specified. see electrical specifications for details. for a slow rise time, see figure 12-6 . two delay timers, (pwrt on ost), have been pro- vided which hold the device in reset after a por (dependent upon device configuration) so that all oper- ational parameters have been met prior to releasing the device to resume/begin normal operation. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure oper- ation. if these conditions are not met, the device must be held in reset until the operating conditions are met. brown-out reset may be used to meet the startup con- ditions, or if necessary an external por circuit may be implemented to delay end of reset for as long as needed. figure 12-6: external power-on reset circuit (for slow v dd ramp) 12.5 power-up timer (pwrt) the power-up timer provides a fixed t pwrt time-out on power-up type resets only. for a por, the pwrt is invoked when the por pulse is generated. for a bor, the pwrt is invoked when the device exits the reset condition (v dd rises above bor trippoint). the power- up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrts time delay is designed to allow v dd to rise to an acceptable level. a configuration bit is provided to enable/disable the pwrt for the por only. for a bor the pwrt is always available regardless of the config- uration bit setting. the power-up time delay will vary from chip-to-chip due to v dd , temperature and process variation. see dc parameters for details. 12.6 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over. this ensures that the crystal oscil- lator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on a power-up type reset or a wake-up from sleep. 12.7 programmable brown-out reset (pbor) the programmable brown-out reset module is used to generate a reset when the supply voltage falls below a specified trip voltage. the trip voltage is configurable to any one of four voltages provided by the borv<1:0> configuration word bits. configuration bit, boden, can disable (if clear/pro- grammed) or enable (if set) the brown-out reset cir- cuitry. if v dd falls below the specified trippoint for longer than t bor , (parameter #35), the brown-out situation will reset the chip. a reset may not occur if v dd falls below the trippoint for less than t bor . the chip will remain in brown-out reset until v dd rises above v bor . the power-up timer will be invoked at that point and will keep the chip in reset an additional t pwrt . if v dd drops below v bor while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be re-initialized. once v dd rises above v bor , the power-up timer will again begin a t pwrt time delay. even though the pwrt is always enabled when brown-out is enabled, the pwrt config- uration word bit should be cleared (enabled) when brown-out is enabled. note 1: external power-on reset circuit is required only if v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k w is recommended to make sure that voltage drop across r does not violate the devices electrical specification. 3: r1 = 100 w to 1 k w will limit any current flowing into mclr from external capacitor c in the event of mclr/ v pp pin break- down due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic16c717/770/771 v dd
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 131 12.8 time-out sequence on power-up, the time-out sequence is as follows: first pwrt time-out is invoked by the por pulse. when the pwrt delay expires, the oscillator start-up timer is activated. the total time-out will vary based on oscilla- tor configuration and the status of the pwrt. for example, in rc mode with the pwrt disabled, there will be no time-out at all. figure 12-7 , figure 12-8 , figure 12-9 and figure 12-10 depict time-out sequences on power-up. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. then bringing mclr high will begin execution immediately ( figure 12-9 ). this is useful for testing purposes or to synchronize more than one picmicro microcontroller operating in parallel. ta bl e 1 2 - 5 shows the reset conditions for some special function registers, while ta bl e 1 2 - 6 shows the reset conditions for all the registers. 12.9 power control/status register (pcon) the power control/status register, pcon, has two status bits that provide indication of which power-up type reset occurred. bit0 is brown-out reset status bit, bor . bit bor is set on a power-on reset. it must then be set by the user and checked on subsequent resets to see if bit bor cleared, indicating a bor occurred. however, if the brown-out circuitry is disabled, the bor bit is a "dont care" bit and is considered unknown upon a por. bit1 is por (power-on reset status bit). it is cleared on a power-on reset and unaffected otherwise. the user must set this bit following a power-on reset. table 12-3: time-out in various situations table 12-4: status bits and their significance table 12-5: reset condition for special registers oscillator configuration power-up brown-out wake-up from sleep pwrte = 0 pwrte = 1 xt, hs, lp t pwrt + 1024t osc 1024t osc t pwrt + 1024t osc 1024t osc ec, er, intrc t pwrt t pwrt por bor to pd 0111 power-on reset 0x0x illegal, to is set on por 0xx0 illegal, pd is set on por 1011 brown-out reset 1101 wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- 1-01 mclr reset during normal operation 000h 000u uuuu ---- 1-uu mclr reset during sleep 000h 0001 0uuu ---- 1-uu wdt reset 000h 0000 1uuu ---- 1-uu wdt wake-up pc + 1 uuu0 0uuu ---- u-uu brown-out reset 000h 0001 1uuu ---- 1-u0 interrupt wake-up from sleep, gie = 0 pc + 1 uuu1 0uuu ---- u-uu interrupt wake-up from sleep, gie = 1 0004h uuu1 0uuu ---- u-uu legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
pic16c717/770/771 ds41120a-page 132 advanced information ? 1999 microchip technology inc. table 12-6: initialization conditions for all registers register power-on reset or brown-out reset mclr reset or wdt reset wake-up via wdt or interrupt w xxxx xxxx uuuu uuuu uuuu uuuu indf 0000 0000 uuuu uuuu uuuu uuuu tmr0 xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000h 0000h pc + 1 (1) status 0001 1xxx 000q quuu (2) uuuq quuu (2) fsr xxxx xxxx uuuu uuuu uuuu uuuu porta xxxx 0000 uuuu 0000 uuuu uuuu portb xxxx xx00 uuuu uu00 uuuu uu00 pclath ---0 0000 ---0 0000 ---u uuuu intcon 0000 000x 0000 000u uuuu uuqq pir1 -0-- 0000 -0-- 0000 -0-- uuuu pir2 0--- 0--- 0--- 0--- q--- q--- tmr1l xxxx xxxx uuuu uuuu uuuu uuuu tmr1h xxxx xxxx uuuu uuuu uuuu uuuu t1con --00 0000 --uu uuuu --uu uuuu tmr2 0000 0000 0000 0000 uuuu uuuu t2con -000 0000 -000 0000 -uuu uuuu sspbuf xxxx xxxx uuuu uuuu uuuu uuuu sspcon 0000 0000 0000 0000 uuuu uuuu ccpr1l xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 0000 0000 0000 0000 uuuu uuuu adresh xxxx xxxx uuuu uuuu uuuu uuuu adcon0 0000 0000 0000 0000 uuuu uuuu option_reg 1111 1111 1111 1111 uuuu uuuu trisa 1111 1111 1111 1111 uuuu uuuu trisb 1111 1111 1111 1111 uuuu uuuu pie1 -0-- 0000 -0-- 0000 -u-- uuuu pie2 0--- 0--- 0--- 0--- u--- u--- pcon ---- 1-qq ---- 1-uu ---- u-uu pr2 1111 1111 1111 1111 1111 1111 sspadd 0000 0000 0000 0000 uuuu uuuu sspstat 0000 0000 0000 0000 uuuu uuuu wpub 1111 1111 1111 1111 uuuu uuuu iocb 1111 0000 1111 0000 uuuu uuuu p1del 0000 0000 0000 0000 uuuu uuuu refcon 0000 ---- 0000 ---- uuuu ---- legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 2: see ta bl e 1 2 - 5 for reset value for specific condition.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 133 figure 12-7: time-out sequence on power-up (mclr tied to v dd ) lvdcon --00 0101 --00 0101 --uu uuuu ansel 1111 1111 1111 1111 uuuu uuuu adresl xxxx xxxx uuuu uuuu uuuu uuuu adcon1 0000 000 0000 0000 uuuu uuuu pmdatl xxxx xxxx uuuu uuuu uuuu uuuu pmadrl xxxx xxxx uuuu uuuu uuuu uuuu pmdath --xx xxxx --uu uuuu --uu uuuu pmadrh ---- xxxx ---- uuuu ---- uuuu pmcon1 1--- ---0 1--- ---0 1--- ---0 table 12-6: initialization conditions for all registers (continued) register power-on reset or brown-out reset mclr reset or wdt reset wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 2: see ta bl e 1 2 - 5 for reset value for specific condition. t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset
pic16c717/770/771 ds41120a-page 134 advanced information ? 1999 microchip technology inc. figure 12-8: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 12-9: time-out sequence on power-up (mclr not tied to v dd ): case 2 figure 12-10: slow v dd rise time (mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset 0v 5v t pwrt t ost note 1: time dependent on oscillator circuit (1)
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 135 12.10 interrupts the devices have up to 11 sources of interrupt. the interrupt control register (intcon) records individual interrupt requests in flag bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>), enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. when bit gie is enabled and an interrupts flag bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be dis- abled through their corresponding enable bits in vari- ous registers. individual interrupt bits are set, regardless of the status of the gie bit. the gie bit is cleared on reset. the return from interrupt instruction, retfie , exits the interrupt routine as well as sets the gie bit, which re-enables interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. the peripheral interrupt flags are contained in the spe- cial function registers pir1 and pir2. the correspond- ing interrupt enable bits are contained in special function registers pie1 and pie2, and the peripheral interrupt enable bit is contained in special function reg- ister intcon. when an interrupt is responded to, the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with 0004h. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs. the latency is the same for one or two cycle instructions. individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the gie bit figure 12-11: interrupt logic note: individual interrupt flag bits are set regard- less of the status of their corresponding mask bit or the gie bit. adif adie sspif sspie ccp1if ccp1ie tmr2if tmr2ie tmr1if tmr1ie t0if t0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu lv d if lv d ie bclie bclif
pic16c717/770/771 ds41120a-page 136 advanced information ? 1999 microchip technology inc. 12.10.1 int interrupt external interrupt on rb0/int pin is edge triggered: either rising if bit intedg (option_reg<6>) is set, or falling, if the intedg bit is clear. when a valid edge appears on the rb0/int pin, flag bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service rou- tine before re-enabling this interrupt. the int interrupt can wake-up the processor from sleep, if bit inte was set prior to going into sleep. the status of global inter- rupt enable bit gie decides whether or not the proces- sor branches to the interrupt vector following wake-up. see section 12.13 for details on sleep mode. 12.10.2 tmr0 interrupt an overflow (ffh ? 00h) in the tmr0 register will set flag bit t0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>). ( section 2.2.2.3 ) 12.10.3 portb intcon change an input change on portb<7:0> sets flag bit rbif (intcon<0>). the portb pin(s) which can individu- ally generate interrupt is selectable in the iocb regis- ter. the interrupt can be enabled/disabled by setting/ clearing enable bit rbie (intcon<4>). ( section 2.2.2.3 ) 12.11 context saving during interrupts during an interrupt, only the pc is saved on the stack. at the very least, w and status should be saved to preserve the context for the interrupted program. all registers that may be corrupted by the isr, such as pclath or fsr, should be saved. example 12-1 stores and restores the status, w and pclath registers. the register, w_temp, is defined in common ram, the last 16 bytes of each bank that may be accessed from any bank. the status_temp and pclath_temp are defined in bank 0. the example: a) stores the w register. b) stores the status register in bank 0. c) stores the pclath register in bank 0. d) executes the isr code. e) restores the pclath register. f) restores the status register g) restores w. note that w_temp, status_temp and pclath_temp are defined in the common ram area (70h - 7fh) to avoid register bank switching during con- text save and restore. example 12-1: saving status, w, and pclath registers in ram #define w_temp 0x70 #define status_temp 0x71 #define pclath_temp 0x72 org 0x04 ; start at interrupt vector movwf w_temp ; save w register movf status,w movwf status_temp ; save status movf pclath,w movwf pclath_temp ; save pclath : (interrupt service routine) : movf pclath_temp,w movwf pclath movf status_temp,w movwf status swapf w_temp,f ; swapf w_temp,w ; swapf loads w without affecting status flags retfie
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 137 12.12 w atchdog timer (wdt) the watchdog timer is a free running on-chip rc oscil- lator, which does not require any external components. this oscillator is in dependent from the processor clock. the wdt will run, even if the main clock of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the to bit in the status register will be cleared upon a watchdog timer time-out. the wdt can be permanently disabled by program- ming the configuration bit wdte ( section 12.1 )0. wdt time-out period values may be found in the elec- trical specifications. values for the wdt prescaler may be assigned using the option_reg register. . figure 12-12: watchdog timer block diagram table 12-7: summary of watchdog timer registers note: the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and prevent it from timing out and generating a device reset condition. note: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared, but the prescaler assignment is not changed. from tmr0 clock source ( figure 5-2 ) to t m r 0 ( figure 5-2 ) postscaler wdt timer wdt enable bit (2) 0 1 m u x psa 8 - to - 1 mux ps<2:0> (1) 0 1 mux psa (1) wdt time-out note 1: psa and ps<2:0> are bits in the option_reg register. 8 2: wdte bit in the configuration word. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h config. bits (1) boden mclre pwrte wdte fosc2 fosc1 fosc0 81h,181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer. note 1: see figure 12-1 for the full description of the configuration word bits.
pic16c717/770/771 ds41120a-page 138 advanced information ? 1999 microchip technology inc. 12.13 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (status<3>) is cleared, the to (status<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had, before the sleep instruction was executed (driving high, low, or hi-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd , or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d, disable external clocks. pull all i/o pins, that are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should be considered. 12.13.1 wake-up from sleep the device can wake up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change, or some peripheral interrupts. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a "wake-up". the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the following peripheral interrupts can wake the device from sleep: 1. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 2. ccp capture mode interrupt. 3. special event trigger (timer1 in asynchronous mode using an external clock). 4. ssp (start/stop) bit detect interrupt. 5. ssp transmit or receive in slave mode (spi/i 2 c). 6. a/d conversion (when a/d clock source is rc). 7. low-voltage detect. other peripherals cannot generate interrupts since dur- ing sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 12.13.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will com- plete as a nop. therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. ? if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will imme- diately wake up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop. to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 139 figure 12-13: wake-up from sleep through interrupt 12.14 program verification/code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 12.15 id locations four memory locations (2000h - 2003h) are designated as id locations where the user can store checksum or other code-identification numbers. these locations are not accessible during normal execution but are read- able and writable during program/verify. it is recom- mended that only the 4 least significant bits of the id location are used. for rom devices, these values are submitted along with the rom code. 12.16 in-circuit serial programming (icsp?) pic16cxxx microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firm- ware to be programmed. for complete details of serial programming, please refer to the in-circuit serial programming (icsp?) guide, (ds30277). q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (3) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle to s t (1) pc+2 note 1: t ost = 1024t osc (drawing not to scale) this delay applies to lp, xt and hs modes only. 2: gie = '1' assumed. in this case after wake- up, the processor jumps to the interrupt routine. if gie = '0', execution will cont inue in-line. 3: clkout is not available in these osc modes, but shown here for timing reference. note: microchip does not recommend code pro- tecting windowed devices.
pic16c717/770/771 ds41120a-page 140 advanced information ? 1999 microchip technology inc. notes:
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 141 13.0 instruction set summary each pic16cxxx instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. the pic16cxx instruction set summary in ta bl e 1 3 - 2 lists byte-oriented , bit-ori- ented , and literal and control operations. ta bl e 1 3 - 1 shows the opcode field descriptions. for byte-oriented instructions, 'f' represents a file reg- ister designator and 'd' represents a destination desig- nator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. for literal and control operations, 'k' represents an eight or eleven bit constant or literal value. table 13-1: opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop. one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 m s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 m s. ta bl e 1 3 - 2 lists the instructions recognized by the mpasm assembler. figure 13-1 shows the general formats that the instruc- tions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. figure 13-1: general format for instructions a description of each instruction is available in the picmicro? mid-range reference manual, (ds33023). field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in file register f. default is d = 1 pc program counter to time-out bit pd power-down bit note: to maintain upward compatibility with future pic16cxxx products, do not use the option and tris instructions. byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16c717/770/771 ds41120a-page 142 advanced information ? 1999 microchip technology inc. table 13-2: pic16cxxx instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to , pd z to , pd c,dc,z z note 1: when an i/o register is modified as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 143 13.1 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k ? (w) status affected: c, dc, z description: the contents of the w register are added to the eight bit literal 'k' and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d ? [0,1] operation: (w) + (f) ? (destination) status affected: c, dc, z description: add the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in reg- ister 'f'. andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) ? (w) status affected: z description: the contents of w register are anded with the eight bit literal 'k'. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .and. (f) ? (destination) status affected: z description: and the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 ? (f) status affected: none description: bit 'b' in register 'f' is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 ? (f) status affected: none description: bit 'b' in register 'f' is set.
pic16c717/770/771 ds41120a-page 144 advanced information ? 1999 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit 'b' in register 'f' is '0', the next instruction is executed. if bit 'b' is '1', then the next instruc- tion is discarded and a nop is exe- cuted instead making this a 2t cy instruction. btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit 'b' in register 'f' is '1', the next instruction is executed. if bit 'b', in register 'f', is '0', the next instruction is discarded, and a nop is executed instead, making this a 2t cy instruction. call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<4:3>) ? pc<12:11> status affected: none description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven bit immedi- ate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h ? (f) 1 ? z status affected: z description: the contents of register 'f' are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 145 comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d ? [0,1] operation: (f ) ? (destination) status affected: z description: the contents of register 'f' are complemented. if 'd' is 0, the result is stored in w. if 'd' is 1, the result is stored back in register 'f'. decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d ? [0,1] operation: (f) - 1 ? (destination) status affected: z description: decrement register 'f'. if 'd' is 0, the result is stored in the w regis- ter. if 'd' is 1, the result is stored back in register 'f'. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d ? [0,1] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none description: the contents of register 'f' are decremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in reg- ister 'f'. if the result is 1, the next instruc- tion is executed. if the result is 0, then a nop is executed instead making it a 2t cy instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k ? pc<10:0> pclath<4:3> ? pc<12:11> status affected: none description: goto is an unconditional branch. the eleven bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d ? [0,1] operation: (f) + 1 ? (destination) status affected: z description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in reg- ister 'f'. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d ? [0,1] operation: (f) + 1 ? (destination), skip if result = 0 status affected: none description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in regis- ter 'f'. i f the result is 1, the next instruc- tion is executed. if the result is 0, a nop is executed instead making it a 2t cy instruction.
pic16c717/770/771 ds41120a-page 146 advanced information ? 1999 microchip technology inc. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k ? (w) status affected: z description: the contents of the w register are ored with the eight bit literal 'k'. the result is placed in the w reg- ister. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .or. (f) ? (destination) status affected: z description: inclusive or the w register with register 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in regis- ter 'f'. movf move f syntax: [ label ] movf f,d operands: 0 f 127 d ? [0,1] operation: (f) ? (destination) status affected: z description: the contents of register f are moved to a destination dependant upon the status of d. if d = 0, des- tination is w register. if d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k ? (w) status affected: none description: the eight bit literal 'k' is loaded into w register. the dont cares will assemble as 0s. movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) ? (f) status affected: none description: move data from w register to reg- ister 'f'. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 147 retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two cycle instruction. return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d ? [0,1] operation: see description below status affected: c description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is stored back in register 'f'. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d ? [0,1] operation: see description below status affected: c description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in reg- ister 'f'. sleep syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 13.8 for more details. register f c register f c
pic16c717/770/771 ds41120a-page 148 advanced information ? 1999 microchip technology inc. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ? ( w) status affected: c, dc, z description: the w register is subtracted (2s complement method) from the eight bit literal 'k'. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d ? [0,1] operation: (f) - (w) ? ( destination) status affected: c, dc, z description: subtract (2s complement method) w register from register 'f'. if 'd' is 0, the result is stored in the w regis- ter. if 'd' is 1, the result is stored back in register 'f'. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d ? [0,1] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0, the result is placed in w regis- ter. if 'd' is 1, the result is placed in register 'f'. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k ? ( w) status affected: z description: the contents of the w register are xored with the eight bit lit- eral 'k'. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .xor. (f) ? ( destination) status affected: z description: exclusive or the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'.
? 1999 microchip technology inc. advanced information ds41120a-page 149 pic16c717/770/771 14.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab? ide software ? assemblers/compilers/linkers - mpasm assembler - mplab-c17 and mplab-c18 c compilers - mplink/mplib linker/librarian ? simulators - mplab-sim software simulator ?emulators - mplab-ice real-time in-circuit emulator - picmaster ? /picmaster-ce in-circuit emulator - icepic? ? in-circuit debugger - mplab-icd for pic16f877 ? device programmers -pro mate a ii universal programmer - picstart a plus entry-level prototype programmer ? low-cost demonstration boards - simice - picdem-1 - picdem-2 - picdem-3 - picdem-17 - seeval a -k ee l oq a 14.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows a -based applica- tion which contains: ? multiple functionality -editor - simulator - programmer (sold separately) - emulator (sold separately) ? a full featured editor ? a project manager ? customizable tool bar and key mapping ? a status bar ? on-line help mplab allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to picmicro tools (automatically updates all project information) ? debug using: - source files - absolute listing file - object code the ability to use mplab with microchips simulator, mplab-sim, allows a consistent platform and the abil- ity to easily switch from the cost-effective simulator to the full featured emulator with minimal retraining. 14.2 mpasm assembler mpasm is a full featured universal macro assembler for all picmicro mcus. it can produce absolute code directly in the form of hex files for device program- mers, or it can generate relocatable objects for mplink. mpasm has a command line interface and a windows shell and can be used as a standalone application on a windows 3.x or greater system. mpasm generates relocatable object files, intel standard hex files, map files to detail memory usage and symbol reference, an absolute lst file which contains source lines and gen- erated machine code, and a cod file for mplab debugging. mpasm features include: ? mpasm and mplink are integrated into mplab projects. ? mpasm allows user defined macros to be created for streamlined assembly. ? mpasm allows conditional assembly for multi pur- pose source files. ? mpasm directives allow complete control over the assembly process. 14.3 mplab-c17 and mplab-c18 c compilers the mplab-c17 and mplab-c18 code development systems are complete ansi c compilers and inte- grated development environments for microchips pic17cxxx and pic18cxxx family of microcontrol- lers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display.
pic16c717/770/771 ds41120a-page 150 advanced information ? 1999 microchip technology inc. 14.4 mplink/mplib linker/librarian mplink is a relocatable linker for mpasm and mplab-c17 and mplab-c18. it can link relocatable objects from assembly or c source files along with pre- compiled libraries using directives from a linker script. mplib is a librarian for pre-compiled code to be used with mplink. when a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application. this allows large libraries to be used efficiently in many dif- ferent applications. mplib manages the creation and modification of library files. mplink features include: ? mplink works with mpasm and mplab-c17 and mplab-c18. ? mplink allows all memory areas to be defined as sections to provide link-time flexibility. mplib features include: ? mplib makes linking easier because single librar- ies can be included instead of many smaller files. ? mplib helps keep code maintainable by grouping related modules together. ? mplib commands allow libraries to be created and modules to be added, listed, replaced, deleted, or extracted. 14.5 mplab-sim software simulator the mplab-sim software simulator allows code development in a pc host environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file or user-defined key press to any of the pins. the execution can be performed in single step, execute until break, or trace mode. mplab-sim fully supports symbolic debugging using mplab-c17 and mplab-c18 and mpasm. the soft- ware simulator offers the flexibility to develop and debug code outside of the laboratory environment mak- ing it an excellent multi-project software development tool. 14.6 mplab-ice high performance universal in-circuit emulator with mplab ide the mplab-ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). software control of mplab-ice is provided by the mplab integrated development environment (ide), which allows editing, make and download, and source debugging from a single environment. interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- cessors. the universal architecture of the mplab-ice allows expansion to support new picmicro microcon- trollers. the mplab-ice emulator system has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive devel- opment tools. the pc platform and microsoft ? windows 3.x/95/98 environment were chosen to best make these features available to you, the end user. mplab-ice 2000 is a full-featured emulator system with enhanced trace, trigger, and data monitoring fea- tures. both systems use the same processor modules and will operate across the full operating speed range of the picmicro mcu. 14.7 picmaster/picmaster ce the picmaster system from microchip technology is a full-featured, professional quality emulator system. this flexible in-circuit emulator provides a high-quality, universal platform for emulating microchip 8-bit picmicro microcontrollers (mcus). picmaster sys- tems are sold worldwide, with a ce compliant model available for european union (eu) countries. 14.8 icepic icepic is a low-cost in-circuit emulation solution for the microchip technology pic16c5x, pic16c6x, pic16c7x, and pic16cxxx families of 8-bit one-time- programmable (otp) microcontrollers. the modular system can support different subsets of pic16c5x or pic16cxxx products through the use of interchangeable personality modules or daughter boards. the emulator is capable of emulating without target application circuitry being present. 14.9 mplab-icd in-circuit debugger microchip's in-circuit debugger, mplab-icd, is a pow- erful, low-cost run-time development tool. this tool is based on the flash pic16f877 and can be used to develop for this and other picmicro microcontrollers from the pic16cxxx family. mplab-icd utilizes the in-circuit debugging capability built into the pic16f87x. this feature, along with microchip's in-cir- cuit serial programming protocol, offers cost-effective in-circuit flash programming and debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. running at full speed enables testing hardware in real-time. the mplab-icd is also a programmer for the flash pic16f87x family.
? 1999 microchip technology inc. advanced information ds41120a-page 151 pic16c717/770/771 14.10 pro mate ii universal programmer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. pro mate ii is ce compliant. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode the pro mate ii can read, verify or program picmicro devices. it can also set code-protect bits in this mode. 14.11 picstart plus entry level development system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and efficient. picstart plus supports all picmicro devices with up to 40 pins. larger pin count devices such as the pic16c92x, and pic17c76x may be supported with an adapter socket. picstart plus is ce compliant. 14.12 simice entry-level hardware simulator simice is an entry-level hardware development sys- tem designed to operate in a pc-based environment with microchips simulator mplab-sim. both simice and mplab-sim run under microchip technologys mplab integrated development environment (ide) software. specifically, simice provides hardware sim- ulation for microchips pic12c5xx, pic12ce5xx, and pic16c5x families of picmicro 8-bit microcontrollers. simice works in conjunction with mplab-sim to pro- vide non-real-time i/o port emulation. simice enables a developer to run simulator code for driving the target system. in addition, the target system can provide input to the simulator code. this capability allows for simple and interactive debugging without having to manually generate mplab-sim stimulus files. simice is a valu- able debugging tool for entry-level system develop- ment. 14.13 picdem-1 low-cost picmicro demonstration board the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample microcontrollers provided with the picdem-1 board, on a pro mate ii or picstart-plus programmer, and easily test firm- ware. the user can also connect the picdem-1 board to the mplab-ice emulator and download the firmware to the emulator for testing. additional proto- type area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 14.14 picdem-2 low-cost pic16cxx demonstration board the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-plus, and easily test firmware. the mplab-ice emulator may also be used with the picdem-2 board to test firmware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 14.15 picdem-3 low-cost pic16cxxx demonstration board the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test firmware. the mplab-ice emulator may also be used with the picdem-3 board to test firm- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the lcd signals.
pic16c717/770/771 ds41120a-page 152 advanced information ? 1999 microchip technology inc. 14.16 picdem-17 the picdem-17 is an evaluation board that demon- strates the capabilities of several microchip microcon- trollers, including pic17c752, pic17c756, pic17c762, and pic17c766. all necessary hardware is included to run basic demo programs, which are sup- plied on a 3.5-inch disk. a programmed sample is included, and the user may erase it and program it with the other sample programs using the pro mate ii or picstart plus device programmers and easily debug and test the sample code. in addition, picdem-17 sup- ports down-loading of programs to and executing out of external flash memory on board. the picdem-17 is also usable with the mplab-ice or picmaster emu- lator, and all of the sample programs can be run and modified using either emulator. additionally, a gener- ous prototype area is available for user hardware. 14.17 seeval evaluation and programming system the seeval seeprom designers kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade- off analysis and reliability calculations. the total kit can significantly reduce time-to-market and result in an optimized system. 14.18 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
? 1999 microchip technology inc. advanced information ds41120a-page 153 pic16c717/770/771 table 14-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment mplab ? c17 compiler mplab ? c18 compiler mpasm/mplink emulators mplab ?-ice ** picmaster/picmaster-ce icepic ? low-cost in-circuit emulator debugger mplab-icd in-circuit debugger * * programmers picstart a plus low-cost universal dev. kit ** pro mate a ii universal programmer ** demo boards and eval kits simice picdem-1 ? picdem-2 ? ? picdem-3 picdem-14a picdem-17 k ee l oq ? evaluation kit k ee l oq transponder kit microid ? programmers kit 125 khz microid developers kit 125 khz anticollision microid developers kit 13.56 mhz anticollision microid developers kit mcp2510 can developers kit * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab-icd in-circuit deb ugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77 ** contact microchip technology inc. for availability date. ? development tool is available on select devices.
pic16c717/770/771 ds41120a-page 154 advanced information ? 1999 microchip technology inc. notes:
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 155 15.0 electrical characteristics absolute maximum ratings ? ambient temperature under bias................................................................................................. ............... . -55 to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr and ra4)........................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ............................................................................................................ -0.3 to +7.5v maximum voltage between av dd and v dd pins ................................................................................................................. 0.3v maximum voltage between av ss and v ss pins ................................................................................................................. 0.3v voltage on mclr with respect to v ss ........................................................................................................ -0.3v to +8.5v voltage on ra4 with respect to vss ............................................................................................. ............ -0.3v to +10.5v total power dissipation (note 1)............................................................................................... .................................1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by porta and portb (combined) .................................................................................200 ma maximum current sourced by porta and portb (combined).......................................................................... ..200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd - v oh ) x i oh } + ? (v o l x i ol ). ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c717/770/771 ds41120a-page 156 advanced information ? 1999 microchip technology inc. figure 15-1: pic16c717/770/771 voltage-frequency graph, -40 c t a +85 c figure 15-2: pic16lc717/770/771 voltage-frequency graph, 0 c t a +70 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 note 1: the shaded region indicates the permissible combinations of voltage and frequency.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 157 figure 15-3: pic16lc717/770/771 voltage-frequency graph, -40 c t a 0 c, +70 c t a +85 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 note 1: the shaded region indicates the permissible combinations of voltage and frequency.
pic16c717/770/771 ds41120a-page 158 advanced information ? 1999 microchip technology inc. 15.1 dc characteristics: pic16c717/770/771 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial and 0c t a +70c for commercial param no. sym characteristic min typ? max units conditions d001 v dd supply voltage 4.0 5.5 v d002* v dr ram data retention voltage (1) 1.5v d003 v por v dd start voltage to ensure internal power-on reset signal v ss v see section on power-on reset for details d004* s vdd v dd rise rate to ensure internal power- on reset signal 0.05 v/ms see section on power-on reset for details. pwrt enabled d010 i dd supply current (2) tbd tbd tbd tbd ma ma ma ma f osc = 20 mhz, v dd = 5.5v* f osc = 20 mhz, v dd = 4.0v f osc = 4 mhz, v dd = 4.0v* f osc = 32 khz, v dd = 4.0v d020 d020a i pd power-down current (3) 1.5 1.5 tbd 16 19 ma m a m a v dd = 5.5v, 0 c to +70 c* v dd = 4.0v, 0 c to +70 c v dd = 4.0v, -40 c to +85 c module differential current (5) d021 d i wdt watchdog timer 6.0 20 m av dd = 4.0v d023b* d i bg (6) bandgap voltage generator 40 m atbd m av dd = 4.0v d025* d i t 1 osc timer1 oscillator 5 9 m av dd = 4.0v d026* d i ad a/d converter 300 m av dd = 5.5v, a/d on, not converting d i lvd low voltage detect 10 tbd m av dd = 4.0v* d i pbor programmable brown-out reset 10 tbd m a pbor enabled, v dd = 5.0v* d i vrh voltage reference high 70 tbd m av dd = 5.0v, no load on vrh* d i vrl voltage reference low 70 tbd m av dd = 4.0v, no load on vrl* 1a fosc lp oscillator, operating freq. intrc oscillator operating freq. er oscillator operating freq. xt oscillator operating freq. hs oscillator operating freq. 9 tbd 0 0 4 37 37 200 tbd 4 20 khz mhz mhz mhz mhz mhz mhz all temperatures all temperatures, oscf = 1 all temperatures, oscf = 0 all temperatures, oscf = 1 all temperatures, oscf = 0 all temperatures all temperatures * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consump- tion. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: for er osc configuration, current through rext is not included. the current through the resistor can be estimated by the for- mula ir = tbd with rext in kohm. 5: the d current is the additional current consumed when the peripheral is enabled. this current should be added to the base (i pd or i dd ) current. 6: the bandgap voltage reference provides 1.22v nominal to the vrl, vrh, lvd and bor circuits. when calculating current con- sumption use the following formula: d i vrl + d i vrh + d i lvd + d i bor + d i bg . any of the d i vrl , d i vrh , d i lvd or d i bor can be 0.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 159 15.2 dc characteristics: pic16lc717/770/771 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial and 0c t a +70c for commercial param no. sym characteristic min typ? max units conditions d001 v dd supply voltage 2.5 5.5 v d002* v dr ram data retention voltage (1) 1.5 v d003 v por v dd start voltage to ensure internal power-on reset signal v ss v see section on power-on reset for details d004* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 v/ms see section on power-on reset for details. pwrt enabled d010 supply current (2) i dd tbd tbd tbd tbd tbd ma ma ma ma ma f osc = 20 mhz, v dd = 5.5v* f osc = 20 mhz, v dd = 4.0v f osc = 10 mhz, v dd = 3.0v f osc = 4 mhz, v dd = 2.5v f osc = 32 khz, v dd = 2.5v d020 d020a i pd power-down current (3) tbd 1.5 1.5 0.9 0.9 tbd 16 19 5 5 m a m a m a m a m a v dd = 5.5v, 0 c to +70 c v dd = 4.0v, 0 c to +70 c v dd = 4.0v, -40 c to +85 c v dd = 2.5v, 0 c to +70 c v dd = 3.0v, -40 c to +85 c module differential current (5) d021 d023b* d i wdt d ibg watchdog timer bandgap voltage generator 6 40 20 tbd m a m a v dd = 3.0v v dd = 3.0v d025* d i t 1 osc timer1 oscillator 1.5 3 m av dd = 3.0v d026* d i ad a/d converter 300 m av dd = 5.5v, a/d on, not converting d i lvd low voltage detect 10 tbd m av dd = 4.0v* d i pbor programmable brown-out reset 10 tbd m a pbor enabled, v dd = 5.0v* d i vrh voltage reference high 70 tbd m av dd = 5.0v, no load on vrh* d i vrl voltage reference low 70 tbd m av dd = 4.0v, no load on vrl* 1a fosc lp oscillator, operating freq. intrc oscillator operating freq. er oscillator operating freq. xt oscillator operating freq. hs oscillator operating freq. 9 tbd 0 0 4 37 37 200 tbd 4 20 khz mhz mhz mhz mhz mhz mhz all temperatures all temperatures, oscf = 1 all temperatures, oscf = 0 all temperatures, oscf = 1 all temperatures, oscf = 0 all temperatures all temperatures * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current con- sumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: for er osc configuration, current through rext is not included. the current through the resistor can be estimated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: the d current is the additional current consumed when the peripheral is enabled. this current should be added to the base (i pd or i dd ) current.
pic16c717/770/771 ds41120a-page 160 advanced information ? 1999 microchip technology inc. 15.3 dc characteristics: pic16c717/770/771 & pic16lc717/770/771 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial and 0c t a +70c for commercial operating voltage v dd range as described in dc spec section 15.1 and section 15.2 . param no. sym characteristic min typ? max units conditions input low voltage v il i/o ports d030 with ttl buffer v ss 0.15v dd v for entire v dd range d030a v ss 0.8v v 4.5v v dd 5.5v d031 with schmitt trigger buffer v ss 0.2v dd v for entire v dd range d032 mclr v ss 0.2v dd v d033 osc1 (in xt, hs, lp and ec) v ss 0.3v dd v input high voltage v ih i/o ports d040 with ttl buffer 2.0 v dd v4.5v v dd 5.5v d040a (0.25v dd + 0.8v) v dd v for entire v dd range d041 with schmitt trigger buffer 0.8v dd v dd v for entire v dd range d042 mclr 0.8v dd v dd v d042a osc1 (xt, hs, lp and ec) 0.7v dd v dd v d070 i purb portb weak pull-up current per pin 50 250 400 m av dd = 5v, v pin = v ss input leakage current (1,2) d060 i il i/o ports (with digital functions) 1 m a vss v pin v dd , pin at hi-imped- ance d060a i il i/o ports (with analog functions) 100 na vss v pin v dd , pin at hi-imped- ance d061 ra5/mclr /v pp 5 m a vss v pin v dd d063 osc1 5 m a vss v pin v dd , xt, hs, lp and ec osc configuration output low voltage d080 v ol i/o ports 0.6 v i ol = 8.5 ma, v dd = 4.5v output high voltage d090 v oh i/o ports (2) v dd - 0.7 v i oh = -3.0 ma, v dd = 4.5v d150* v od open-drain high voltage 10.5 v ra4 pin capacitive loading specs on out- put pins* d100 cosc2 osc2 pin 15 pf in xt, hs and lp modes when exter- nal clock is used to drive osc1. d101 d102 c io c b all i/o pins and osc2 (in rc mode) scl, sda in i 2 c mode 50 400 pf pf c vrh v rh pin 200 pf v rh output enabled c vrl v rl pin 200 pf v rl output enabled * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent nor- mal operating conditions. higher leakage current may be measured at different input voltages. 2: negative current is defined as current sourced by the pin.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 161 15.4 ac characteristics: pic16c717/770/771 & pic16lc717/770/771 (commercial, industrial) 15.4.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: figure 15-4: load conditions 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t ffrequency ttime lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l =464 w c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 load condition 2
pic16c717/770/771 ds41120a-page 162 advanced information ? 1999 microchip technology inc. 15.4.2 timing diagrams and specifications figure 15-5: clkout and i/o timing table 15-1: clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 75 200 ns note 1 11* tosh2ckh osc1 - to clkout - 75 200 ns note 1 12* tckr clkout rise time 35 100 ns note 1 13* tckf clkout fall time 35 100 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - 0.25t cy + 25 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 50 150 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) pic16 c 717/770/771 100 ns pic16 lc 717/770/771 200 ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) 0 ns 20* tior port output rise time pic16 c 717/770/771 1025ns pic16 lc 717/770/771 60ns 21* tiof port output fall time pic16 c 717/770/771 1025ns pic16 lc 717/770/771 60ns 22??* tinp int pin high or low time t cy ns 23??* trbp rb7:rb0 change int high or low time t cy ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 15-4 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 163 figure 15-6: external clock timing osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 table 15-2: external clock timing requirements parameter no. sym characteristic min typ? max units conditions 1a f osc external clkin frequency (note 1) dc 4 mhz xt osc mode dc 20 mhz ec osc mode dc 20 mhz hs osc mode dc 200 khz lp osc mode oscillator frequency (note 1) 0.1 4 mhz xt osc mode 4 5 20 200 mhz khz hs osc mode lp osc mode 1t osc external clkin period (note 1) 250 ns xt and rc osc mode 50 ns ec osc mode 50 ns hs osc mode 5 m s lp osc mode oscillator period (note 1) 250 10,000 ns xt osc mode 50 250 ns hs osc mode 5 m s lp osc mode 2t cy instruction cycle time (note 1) 200 t cy dc ns t cy = 4/f osc 3* tosl, to s h external clock in (osc1) high or low time 100 ns xt oscillator 2.5 m s lp oscillator 15 ns hs oscillator ec oscillator 4* tosr, to s f external clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator ec oscillator * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices.
pic16c717/770/771 ds41120a-page 164 advanced information ? 1999 microchip technology inc. table 15-3: calibrated internal rc frequencies - pic16c717/770/771 and pic16lc717/770/771 figure 15-7: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 15-8: brown-out reset timing ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial), C40 c t a +85 c (industrial), operating voltage v dd range is described in section 15.1 and section 15.2 parameter no. sym characteristic min* typ (1) max* units conditions internal calibrated rc frequency 3.65 4.00 4.28 mhz v dd = 5.0v internal calibrated rc frequency 3.55 4.00 4.31 mhz v dd = 2.5v * these parameters are characterized but not tested. note 1: data in the typical (typ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 15-4 for load conditions. v dd bv dd 35
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 165 table 15-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements figure 15-9: brown-out reset characteristics figure 15-10: timer0 and timer1 external clock timings parameter no. sym characteristic min typ? max units conditions 30* t mcl mclr pulse width (low) 2 m sv dd = 5v, -40c to +85c 31* t wdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, -40c to +85c 32* t ost oscillation start-up timer period 1024 t osc t osc = osc1 period 33* t pwrt power up timer period 28 72 132 ms v dd = 5v, -40c to +85c 34* t ioz i/o hi-impedance from mclr low or watchdog timer reset 2.1 m s 35* t bor brown-out reset pulse width 100 m sv dd v bor (d005) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v bor reset (due to bor) v dd (device in brown-out reset) (device not in brown-out reset) 72 ms time out note: refer to figure 15-4 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1
pic16c717/770/771 ds41120a-page 166 advanced information ? 1999 microchip technology inc. table 15-5: timer0 and timer1 external clock requirements figure 15-11: enhanced capture/compare/pwm timings (eccp1) param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 42* tt0p t0cki period no prescaler t cy + 40 ns with prescaler greater of: 20 or t cy + 40 n ns n = prescale value (2, 4, ..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 717/770/771 15 ns pic16 lc 717/770/771 25 ns asynchronous pic16 c 717/770/771 30 ns pic16 lc 717/770/771 50 ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 717/770/771 15 ns pic16 lc 717/770/771 25 ns asynchronous pic16 c 717/770/771 30 ns pic16 lc 717/770/771 50 ns 47* tt1p t1cki input period synchronous pic16 c 717/770/771 greater of : 30 or t cy + 40 n ns n = prescale value (1, 2, 4, 8) pic16 lc 717/770/771 greater of : 50 or t cy + 40 n ns n = prescale value (1, 2, 4, 8) asynchronous pic16 c 717/770/771 60 ns pic16 lc 717/770/771 100 ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc 50 khz 48 tcke2tmr1 delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 15-4 for load conditions. rb3/ccp1/p1a (capture mode) 50 51 52 53 54 rb3/ccp1/p1a (compare or pwm mode)
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 167 table 15-6: enhanced capture/compare/pwm requirements (eccp1) param no. sym characteristic min typ? max units conditions 50* tccl ccp1 input low time no prescaler 0.5t cy + 20 ns with prescaler pic16 c 717/770/771 10 ns pic16 lc 717/770/771 20 ns 51* tcch ccp1 input high time no prescaler 0.5t cy + 20 ns with prescaler pic16 c 717/770/771 10 ns pic16 lc 717/770/771 20 ns 52* tccp ccp1 input period 3t cy + 40 n ns n = prescale value (1,4 or 16) 53* tccr ccp1 output fall time pic16 c 717/770/771 1025ns pic16 lc 717/770/771 2545ns 54* tccf ccp1 output fall time pic16 c 717/770/771 1025ns pic16 lc 717/770/771 2545ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16c717/770/771 ds41120a-page 168 advanced information ? 1999 microchip technology inc. 15.5 analog peripherals characteristics: pic16c717/770/771 & pic16lc717/ 770/771 (commercial, industrial) 15.5.1 bandgap module figure 15-12: bandgap start-up time table 15-7: bandgap start-up time parameter no. sym characteristic min typ? max units conditions 36* t bgap bandgap start-up time 30tbd m s defined as the time between the instant that the bandgap is enabled and the moment that the bandgap reference voltage is stable. * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v bgap = 1.2v v bgap enable bandgap bandgap stable t bgap (internal use only)
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 169 15.5.2 low voltage detect module (lvd) table 15-8: low-voltage detect characteristics table 15-9: electrical characteristics: lvd dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial and 0c t a +70c for commercial operating voltage v dd range as described in dc spec section 15.1 and section 15.2 . param no. characteristic symbol min typ? max units conditions d420* lv d vol t ag e lvv = 0100 2.5 2.58 2.66 v lvv = 0101 2.7 2.78 2.86 v lvv = 0110 2.8 2.89 2.98 v lvv = 0111 3.0 3.1 3.2 v lvv = 1000 3.3 3.41 3.52 v lvv = 1001 3.5 3.61 3.72 v lvv = 1010 3.6 3.72 3.84 v lvv = 1011 3.8 3.92 4.04 v lvv = 1100 4.0 4.13 4.26 v lvv = 1101 4.2 4.33 4.46 v lvv = 1110 4.5 4.64 4.78 v d422* lvd voltage temperature coefficient tcv out 15 50 ppm/c d423* lvd voltage supply regulation d v lvd / d v dd 50 m v/v * these parameters are characterized but not tested. note 1: production tested at tamb = 25c. specifications over temperature limits ensured by characterization. v lvd lv d i f v dd (lvdif set by hardware) (lvdif can be cleared in software anytime during the gray area)
pic16c717/770/771 ds41120a-page 170 advanced information ? 1999 microchip technology inc. 15.5.3 programmable brown-out reset module (pbor) table 15-10: dc characteristics: pbor 15.5.4 v ref module table 15-11: dc characteristics: v ref dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial and 0c t a +70c for commercial operating voltage v dd range as described in dc spec section 15.1 and section 15.2 . param no. characteristic symbol min typ max units conditions d005* bor voltage borv<1:0> = 11 v bor 2.5 2.58 2.66 v borv<1:0> = 10 2.7 2.78 2.86 borv<1:0> = 01 4.2 4.33 4.46 borv<1:0> = 00 4.5 4.64 4.78 d006* bor voltage temperature coefficient tcv out 15 50 ppm/c d006a* bor voltage supply regulation d v bor / d v dd 50 m v/v * these parameters are characterized but not tested. dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial and 0c t a +70c for commercial operating voltage v dd range as described in dc spec section 15.1 and section 15.2 . param no. symbol characteristic min typ? max units conditions d400 vrl output voltage 2.0 2.048 2.1 v v dd 3 2.5v vrh 4.0 4.096 4.2 v v dd 3 4.5v d402* tcv out output voltage tempera- ture coefficient 15 50 ppm/c d404* i vrefso external load source 5ma d405* i vrefsi external load sink -5 ma * cl external capacitor load 200 pf d406* d v out / d i out load regulation 1tbd mv/ma isource = 0 ma to 5 ma 1 tbd isink = 0 ma to 5 ma d407* d v out / d v dd supply regulation 50 m v/v * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 171 15.5.5 a/d converter module table 15-12: pic16c770/771 and pic16lc770/771 a/d converter characteristics : param no. sym characteristic min typ? max units conditions a01 n r resolution 12 bits bit min. resolution for a/d is 1 mv, v ref + = av dd = 4.096v, v ref - = av ss = 0v, v ref - v ain v ref + a03 e il integral error tbd v ref + = av dd = 4.096v, v ref - = av ss = 0v, v ref - v ain v ref + a04 e dl differential error tbd no missing codes to 10 bits v ref + = av dd = 4.096v, v ref - = av ss = 0v, v ref - v ain v ref + a06 e off offset error tbd v ref + = av dd = 4.096v, v ref - = av ss = 0v, v ref - v ain v ref + a07 e gn gain error tbd lsb v ref + = av dd = 4.096v, v ref - = av ss = 0v, v ref - v ain v ref + a10 monotonicity guaranteed (3) av ss v ain v ref + a20 v ref reference voltage (v ref + v ref -) 4.096 v dd +0.3v v absolute minimum electrical spec to ensure 12-bit accuracy. a21 v ref + reference v high (a vdd or v ref +) v ref - av dd v min. resolution for a/d is 1 mv a22 v ref - reference v low (a vss or v ref -) av ss v ref + v min. resolution for a/d is 1 mv a25 v ain analog input voltage v refl v refh v a30 z ain recommended impedance of analog voltage source 2.5k w a50 i ref v ref input current (note 2) 10 m a during v ain acquisition. based on differential of v hold to v ain . to charge c hold see section 11.0 . during a/d conversion cycle. * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power down current spec includes any such leakage from the a/d module. 2: v ref input current is from external v ref +, or v ref -, or av ss , or av dd pin, whichever is selected as reference input. 3: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes.
pic16c717/770/771 ds41120a-page 172 advanced information ? 1999 microchip technology inc. figure 15-13: pic16c770/771 and pic16lc770/771 a/d conversion timing (normal mode) table 15-13: pic16c770/771 and pic16lc770/771 a/d conversion requirements parameter no. sym characteristic min typ? max units conditions 130* t ad a/d clock period 1.6 m s tosc based, v ref 3 2.5v 3.0 m s tosc based, v ref full range 130* t ad a/d internal rc oscillator period 3.0 6.0 9.0 m s adcs<1:0> = 11 (rc mode) at v dd = 2.5v 2.0 4.0 6.0 m sat v dd = 5.0v 131* t cnv conversion time (not including acquisition time) (note 1) 13t ad t ad set go bit to new data in a/d result register 132* t acq acquisition time note 2 5* 11.5 m s m s the minimum time is the amplifier settling time. this may be used if the new input voltage has not changed by more than 1lsb (i.e 1mv @ 4.096v) from the last sam- pled voltage (as stated on c hold ). 134* t go q4 to a/d clock start t osc /2 if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 11.6 for minimum conditions. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 11 10 9 3 2 1 0 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1/2 t cy 8 134
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 173 figure 15-14: pic16c770/771 and pic16lc770/771 a/d conversion timing (sleep mode) table 15-14: pic16c770/771 and pic16lc770/771 a/d conversion requirements parameter no. sym characteristic min typ? max units conditions 130* t ad a/d clock period 1.6 m sv ref 3 2.5v tbd m sv ref full range 130* t ad a/d internal rc oscillator period 3.0 6.0 9.0 m s adcs<1:0> = 11 (rc mode) at v dd = 3.0v 2.0 4.0 6.0 m sat v dd = 5.0v 131* t cnv conversion time (not including acquisition time) (note 1) 13t ad 132* t acq acquisition time note 2 5* 11.5 m s m s the minimum time is the amplifier settling time. this may be used if the new input voltage has not changed by more than 1lsb (i.e 1mv @ 4.096v) from the last sam- pled voltage (as stated on c hold ). 134* t go q4 to a/d clock start t osc /2 + t cy if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 11.6 for minimum conditions. 131 130 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 11 9 3 2 1 0 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 134 8 10 132
pic16c717/770/771 ds41120a-page 174 advanced information ? 1999 microchip technology inc. table 15-15: pic16c717 and pic16lc717 a/d converter characteristics : param no. sym characteristic min typ? max units conditions a01 n r resolution 10 bits bit min. resolution for a/d is 4.1 mv, v ref + = av dd = 4.096v, v ref - = av ss = 0v, v ref - v ain v ref + a03 e il integral error tbd v ref + = av dd = 4.096v, v ref - = av ss = 0v, v ref - v ain v ref + a04 e dl differential error tbd no missing codes to 10 bits v ref + = av dd = 4.096v, v ref - = av ss = 0v, v ref - v ain v ref + a06 e off offset error tbd v ref + = av dd = 4.096v, v ref - = av ss = 0v, v ref - v ain v ref + a07 e gn gain error tbd lsb v ref + = av dd = 4.096v, v ref - = av ss = 0v, v ref - v ain v ref + a10 monotonicity guaranteed (3) av ss v ain v ref + a20 v ref reference voltage (v ref + v ref -) 4.096 v dd +0.3v v absolute minimum electrical spec to ensure 10-bit accuracy. a21 v ref + reference v high (a vdd or v ref +) v ref - av dd v min. resolution for a/d is 4.1 mv a22 v ref - reference v low (a vss or v ref -) av ss v ref + v min. resolution for a/d is 4.1 mv a25 v ain analog input voltage v refl v refh v a30 z ain recommended impedance of analog voltage source 2.5k w a50 i ref v ref input current (note 2) 10 m a during v ain acquisition. based on differential of v hold to v ain . to charge c hold see section 11.0 . during a/d conversion cycle. * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than leakage current. the power down current spec includes any such leakage from the a/d module. 2: v ref current is from external v ref +, or v ref -, or av ss , or av dd pin, whichever is selected as reference input. 3: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes.
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 175 figure 15-15: pic16c717 a/d conversion timing (normal mode) table 15-16: pic16c717 and pic16lc717 a/d conversion requirements parameter no. sym characteristic min typ? max units conditions 130* t ad a/d clock period 1.6 m s tosc based, v ref 3 2.5v 3.0 m s tosc based, v ref full range 130* t ad a/d internal rc oscillator period 3.0 6.0 9.0 m s adcs<1:0> = 11 (rc mode) at v dd = 2.5v 2.0 4.0 6.0 m sat v dd = 5.0v 131* t cnv conversion time (not including acquisition time) (note 1) 11t ad t ad set go bit to new data in a/d result register 132* t acq acquisition time note 2 5* 11.5 m s m s the minimum time is the amplifier settling time. this may be used if the new input voltage has not changed by more than 1lsb (i.e 1mv @ 4.096v) from the last sam- pled voltage (as stated on c hold ). 134* t go q4 to a/d clock start t osc /2 if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 11.6 for minimum conditions. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 987 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1/2 t cy 6 134
pic16c717/770/771 ds41120a-page 176 advanced information ? 1999 microchip technology inc. figure 15-16: pic16c717 a/d conversion timing (sleep mode) table 15-17: pic16c717 and pic16lc717 a/d conversion requirements parameter no. sym characteristic min typ? max units conditions 130* t ad a/d clock period 1.6 m sv ref 3 2.5v tbd m sv ref full range 130* t ad a/d internal rc oscillator period 3.0 6.0 9.0 m s adcs<1:0> = 11 (rc mode) at v dd = 3.0v 2.0 4.0 6.0 m sat v dd = 5.0v 131* t cnv conversion time (not including acquisition time) (note 1) 11t ad 132* t acq acquisition time note 2 5* 11.5 m s m s the minimum time is the amplifier settling time. this may be used if the new input voltage has not changed by more than 1lsb (i.e 1mv @ 4.096v) from the last sam- pled voltage (as stated on c hold ). 134* t go q4 to a/d clock start t osc /2 + t cy if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 11.6 for minimum conditions. 131 130 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 9 7 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 134 6 8 132
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 177 16.0 dc and ac characteristics graphs and tables the graphs and tables provided in this section are for design guidance and are not tested . in some graphs or tables, the data presented are out- side specified operating range (i.e., outside specified v dd range). this is for information only . the data presented in this section is a statistical sum- mary of data collected on units from different lots over a period of time and matrix samples. 'typical' repre- sents the mean of the distribution at 25 c. 'max' or 'min' represents (mean + 3 s ) or (mean - 3 s ) respectively, where s is standard deviation, over the whole temper- ature range. graphs and tables not available at this time.
pic16c717/770/771 ds41120a-page 178 advanced information ? 1999 microchip technology inc. notes:
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 179 17.0 packaging information 17.1 package marking information 18-lead soic xxxxxxxxxxxx yywwnnn xxxxxxxxxxxxxxxxx yywwnnn 18-lead pdip example pic16c717/p 9917017 xxxxxxxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxx yywwnnn 18-lead cerdip windowed pic16c717/jw example 9905017 xxxxxxxx 20-lead pdip example legend: mm...m microchip part number information xx...x customer specific information* yy year code (last 2 digits of calendar year) ww w eek code (week of january 1 is week 01) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. xxxxxxxxxxxxxxxxx yywwnnn pic16c770/p 9917017 xxxxxxxxxxxxxxxxx xxxxxxxxxxxx example 9910017 pic16c717/so
pic16c717/770/771 ds41120a-page 180 advanced information ? 1999 microchip technology inc. package marking information (contd) yywwnnn xxxxxxxxxxx xxxxxxxxxxx 20-lead ssop 9917017 20i/ss pic16c770 example xxxxxxxx yywwnnn 20-lead cerdip windowed pic16c770/jw example 9905017 xxxxxxxx 20-lead soic xxxxxxxxxxxxxxxxxxxxxxxx yywwnnn example pic16c771/so 9910017 xxxxxxxxxxxxxxxxxxxxxxxx
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 181 17.2 18-lead plastic dual in-line (p) C 300 mil (pdip) 15 10 5 15 10 5 b mold draft angle bottom 15 10 5 15 10 5 a mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.46 1.14 .070 .058 .045 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 22.99 22.80 22.61 .905 .898 .890 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n e1 c eb b e a p a2 l b1 b a a1 *controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-007
pic16c717/770/771 ds41120a-page 182 advanced information ? 1999 microchip technology inc. 17.3 18-lead ceramic dual in-line with window (jw) C 300 mil (cerdip) 3.30 3.56 3.81 5.33 5.08 4.83 .210 .200 .190 w2 window length .150 .140 .130 w1 window width 10.80 9.78 8.76 .425 .385 .345 eb overall row spacing 0.53 0.47 0.41 .021 .019 .016 b lower lead width 1.52 1.40 1.27 .060 .055 .050 b1 upper lead width 0.30 0.25 0.20 .012 .010 .008 c lead thickness 3.81 3.49 3.18 .150 .138 .125 l tip to seating plane 23.37 22.86 22.35 .920 .900 .880 d overall length 7.49 7.37 7.24 .295 .290 .285 e1 ceramic pkg. width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.76 0.57 0.38 .030 .023 .015 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 4.95 4.64 4.32 .195 .183 .170 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n w2 e1 w1 c eb e p l a2 b b1 a a1 *controlling parameter jedec equivalent: mo-036 drawing no. c04-010
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 183 17.4 18-lead plastic small outline (so) C wide, 300 mil (soic) foot angle f 048048 15 12 0 15 12 0 b mold draft angle bottom 15 12 0 15 12 0 a mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.30 0.27 0.23 .012 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 11.73 11.53 11.33 .462 .454 .446 d overall length 7.59 7.49 7.39 .299 .295 .291 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units l b c f h 45 1 2 d p n b e1 e a a2 a1 a *controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-051
pic16c717/770/771 ds41120a-page 184 advanced information ? 1999 microchip technology inc. 17.5 20-lead plastic dual in-line (p) C 300 mil (pdip) 15 10 5 15 10 5 b mold draft angle bottom 15 10 5 15 10 5 a mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.65 1.52 1.40 .065 .060 .055 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.56 3.30 3.05 .140 .130 .120 l tip to seating plane 26.42 26.24 26.04 1.040 1.033 1.025 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.87 7.49 .325 .310 .295 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n e1 c b eb e a p a2 l b1 b a a1 *controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-019
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 185 17.6 20-lead ceramic dual in-line with window (jw) C 300 mil (cerdip) drawing n ot available
pic16c717/770/771 ds41120a-page 186 advanced information ? 1999 microchip technology inc. 17.7 20-lead plastic small outline (so) C wide, 300 mi (soic) *controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-094 foot angle f 048048 15 12 0 15 12 0 b mold draft angle bottom 15 12 0 15 12 0 a mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 13.00 12.80 12.60 .512 .504 .496 d overall length 7.59 7.49 7.39 .299 .295 .291 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units h l c b 45 f 1 2 d p n b e e1 a a2 a a1
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 187 17.8 20-lead plastic shrink small outline (ss) C 209 mil, 5.30 mm (ssop) 10 5 0 10 5 0 b mold draft angle bottom 10 5 0 10 5 0 a mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 f foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 7.34 7.20 7.06 .289 .284 .278 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.18 7.85 7.59 .322 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.66 .026 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c b f a a2 a a1 *controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per side. jedec equivalent: mo-150 drawing no. c04-072
pic16c717/770/771 ds41120a-page 188 advanced information ? 1999 microchip technology inc. notes:
pic16c717/770/771 ? 1999 microchip technology inc. advanced information ds41120a-page 189 appendix a: revision history appendix b: device differences the differences between the devices in this data sheet are listed in ta b l e b - 1 . version date revision description a 9/16/99 this is a new data sheet. however, the devices described in this data sheet are the upgrades to the devices found in the pic16c7x data sheet , ds30390e. table b-1: device differences difference pic16c717 pic16c770 pic16c771 program memory 2k 2k 4k a/d 6 channels, 10 bits 6 channels, 12 bits 6 channels, 12 bits dedicated av dd and av ss not available available available packages 18-pin pdip, 18-pin windowed cerdip, 18-pin soic, 20-pin ssop 20-pin pdip, 20-pin windowed cerdip, 20-pin soic, 20-pin ssop 20-pin pdip, 20-pin windowed cerdip, 20-pin soic, 20-pin ssop
pic16c717/770/771 ds41120a-page 190 advanced information ? 1999 microchip technology inc. notes:
1999 microchip technology inc. advanced information ds41120a-page 191 pic16c717/770/771 index a a/d .................................................................................... 113 a/d converter enable (adie bit) ................................ 19 adcon0 register..................................................... 113 adcon1 register............................................. 113, 115 adres register ....................................................... 113 block diagram........................................................... 117 configuring analog port............................................ 116 conversion time ........................................................ 123 conversions .............................................................. 119 converter characteristics ................... 169, 170, 171, 174 faster conversion - lower resolution tradeoff ....... 123 internal sampling switch (rss) impedence .............. 121 operation during sleep ............................................ 124 sampling requirements............................................ 121 sampling time .......................................................... 121 source impedance.................................................... 121 special event trigger (ccp)....................................... 57 a/d conversion clock ....................................................... 118 ack ..................................................................................... 78 acknowledge data bit, akd ................................................ 70 acknowledge pulse............................................................. 78 acknowledge sequence enable bit, ake ........................... 70 acknowledge status bit, aks ............................................. 70 ackstat ........................................................................... 92 adcon0 register............................................................. 113 adcon1 register..................................................... 113, 115 adres.............................................................................. 113 adres register ........................................... 13, 14, 113, 124 akd..................................................................................... 70 ake..................................................................................... 70 aks..................................................................................... 70 application note an578, "use of the ssp module in the i2c multi-master environment."................................................. 77 architecture pic16c717/pic16c717 block diagram ....................... 5 pic16c770/771/pic16c770/771 block diagram ......... 6 assembler mpasm assembler................................................... 149 b banking, data memory ................................................. 11, 16 baud rate generator .......................................................... 86 bf ..................................................................... 68, 78, 92, 95 block diagrams baud rate generator.................................................. 86 i 2 c master mode......................................................... 84 i 2 c module .................................................................. 77 ra3:ra0 and ra5 port pins .................... 28, 30, 31, 37 ssp (i 2 c mode) .......................................................... 77 ssp (spi mode).......................................................... 71 bor. see brown-out reset brg .................................................................................... 86 brown-out reset (bor) .................................... 125, 131, 132 buffer full bit, bf ................................................................ 78 buffer full status bit, bf ..................................................... 68 bus arbitration .................................................................. 103 bus collision section ........................................................ 103 bus collision during a restart condition..................... 106 bus collision during a start condition .............................. 104 bus collision during a stop condition .............................. 107 c capture (ccp module) ....................................................... 56 block diagram ............................................................ 56 ccp pin configuration ............................................... 56 ccpr1h:ccpr1l registers ..................................... 56 changing between capture prescalers ..................... 56 software interrupt ....................................................... 56 timer1 mode selection............................................... 56 ccp1con .......................................................................... 15 ccp2con .......................................................................... 15 ccpr1h register......................................................... 13, 15 ccpr1l register ............................................................... 15 ccpr2h register............................................................... 15 ccpr2l register ............................................................... 15 cke .................................................................................... 68 ckp .................................................................................... 69 clock polarity select bit, ckp............................................. 69 code examples loading the sspbuf register .................................... 72 code protection ........................................................ 125, 139 compare (ccp module) ..................................................... 56 block diagram ............................................................ 57 ccp pin configuration ............................................... 56 ccpr1h:ccpr1l registers ..................................... 56 software interrupt ....................................................... 56 special event trigger ........................................... 51, 57 timer1 mode selection............................................... 56 configuration bits ............................................................. 125 d d/a ...................................................................................... 68 data memory ...................................................................... 11 bank select (rp<1:0> bits).................................. 11, 16 general purpose registers ........................................ 11 register file map ....................................................... 12 special function registers......................................... 13 data/address bit, d/a ......................................................... 68 dc characteristics pic16c717/770/771 ................................................. 158 development support ....................................................... 149 device differences............................................................ 189 direct addressing ............................................................... 25 e enhanced capture/compare/pwm (ccp) ccp1 ccpr1h register .............................................. 55 ccpr1l register ............................................... 55 enable (ccp1ie bit)........................................... 19 timer resources ........................................................ 56 enhanced capture/compare/pwm (eccp)....................... 55 external power-on reset circuit....................................... 130 f firmware instructions ....................................................... 141 flowcharts acknowledge .............................................................. 99 master receiver ......................................................... 96 master transmit.......................................................... 93 restart condition........................................................ 90 start condition............................................................ 88 stop condition .......................................................... 101 fsr register .......................................................... 13, 14, 15
pic16c717/770/771 ds41120a-page 192 advanced information 1999 microchip technology inc. g gce .................................................................................... 70 general call address sequence......................................... 83 general call address support ............................................ 83 general call enable bit, gce ............................................. 70 i i/o ports .............................................................................. 27 i 2 c ....................................................................................... 77 i 2 c master mode receiver flowchart ................................. 96 i 2 c master mode reception................................................ 95 i 2 c master mode restart condition .................................... 89 i 2 c mode selection ............................................................. 77 i 2 c module acknowledge flowchart .............................................. 99 acknowledge sequence timing ................................... 98 addressing .................................................................. 78 baud rate generator .................................................. 86 block diagram............................................................. 84 brg block diagram .................................................... 86 brg reset due to sda collision .............................. 105 brg timing ................................................................ 86 bus arbitration .......................................................... 103 bus collision ............................................................. 103 acknowledge..................................................... 103 restart condition .............................................. 106 restart condition timing (case1)..................... 106 restart condition timing (case2)..................... 106 start condition .................................................. 104 start condition timing .............................. 104, 105 stop condition .................................................. 107 stop condition timing (case1)......................... 107 stop condition timing (case2)......................... 107 transmit timing ................................................ 103 bus collision timing................................................... 103 clock arbitration........................................................ 102 clock arbitration timing (master transmit)............... 102 conditions to not give ack pulse ............................... 78 general call address support .................................... 83 master mode ............................................................... 84 master mode 7-bit reception timing ........................... 97 master mode operation .............................................. 85 master mode start condition ...................................... 87 master mode transmission......................................... 92 master mode transmit sequence ............................... 85 master transmit flowchart ......................................... 93 multi-master communication .................................... 103 multi-master mode ...................................................... 85 operation .................................................................... 77 repeat start condition timing ..................................... 89 restart condition flowchart........................................ 90 slave mode ................................................................. 78 slave reception .......................................................... 79 slave transmission..................................................... 79 sspbuf...................................................................... 78 start condition flowchart............................................ 88 stop condition flowchart.......................................... 101 stop condition receive or transmit timing............... 100 stop condition timing ................................................ 100 waveforms for 7-bit reception ................................... 80 waveforms for 7-bit transmission .............................. 80 i 2 c module address register, sspadd............................. 78 i 2 c slave mode ................................................................... 78 id locations .............................................................. 125, 139 in-circuit serial programming (icsp) ....................... 125, 139 indf.................................................................................... 15 indf register ............................................................... 13, 14 indirect addressing ............................................................. 25 fsr register .............................................................. 11 instruction format............................................................. 141 instruction set................................................................... 141 addlw..................................................................... 143 addwf..................................................................... 143 andlw..................................................................... 143 andwf..................................................................... 143 bcf .......................................................................... 143 bsf........................................................................... 143 btfsc ...................................................................... 144 btfss ...................................................................... 144 call......................................................................... 144 clrf ........................................................................ 144 clrw ....................................................................... 144 clrwdt .................................................................. 144 comf ....................................................................... 145 decf ........................................................................ 145 decfsz ................................................................... 145 goto ....................................................................... 145 incf ......................................................................... 145 incfsz..................................................................... 145 iorlw ...................................................................... 146 iorwf...................................................................... 146 movf ....................................................................... 146 movlw .................................................................... 146 movwf .................................................................... 146 nop .......................................................................... 146 retfie ..................................................................... 147 retlw ..................................................................... 147 return................................................................... 147 rlf ........................................................................... 147 rrf .......................................................................... 147 sleep ...................................................................... 147 sublw ..................................................................... 148 subwf..................................................................... 148 swapf ..................................................................... 148 xorlw .................................................................... 148 xorwf .................................................................... 148 summary table ........................................................ 142 intcon .............................................................................. 15 intcon register................................................................ 18 gie bit ........................................................................ 18 inte bit ...................................................................... 18 intf bit ...................................................................... 18 peie bit ...................................................................... 18 rbie bit ...................................................................... 18 rbif bit ................................................................ 18, 35 t0ie bit ....................................................................... 18 t0if bit ....................................................................... 18 inter-integrated circuit (i 2 c) ............................................... 67 internal sampling switch (rss) impedence ....................... 121 interrupt sources ...................................................... 125, 135 block diagram .......................................................... 135 capture complete (ccp)............................................ 56 compare complete (ccp).......................................... 56 rb0/int pin, external............................................... 136 tmr0 overflow................................................... 48, 136 tmr1 overflow..................................................... 49, 51 tmr2 to pr2 match ................................................... 54 tmr2 to pr2 match (pwm) ................................. 53, 58 interrupts synchronous serial port interrupt............................... 20 interrupts, context saving during..................................... 136
1999 microchip technology inc. advanced information ds41120a-page 193 pic16c717/770/771 interrupts, enable bits a/d converter enable (adie bit) ................................ 19 ccp1 enable (ccp1ie bit)................................... 19, 56 global interrupt enable (gie bit) ........................ 18, 135 interrupt on change (rb7:rb4) enable (rbie bit) ............................................................ 18, 136 peripheral interrupt enable (peie bit) ........................ 18 psp read/write enable (pspie bit) .......................... 19 rb0/int enable (inte bit) ......................................... 18 ssp enable (sspie bit) ............................................. 19 tmr0 overflow enable (t0ie bit)............................... 18 tmr1 overflow enable (tmr1ie bit) ......................... 19 tmr2 to pr2 match enable (tmr2ie bit) ................. 19 usart receive enable (rcie bit) ............................ 19 interrupts, flag bits ccp1 flag (ccp1if bit) ............................................. 56 interrupt on change (rb7:rb4) flag (rbif bit) ...................................................... 18, 35, 136 rb0/int flag (intf bit).............................................. 18 tmr0 overflow flag (t0if bit) ........................... 18, 136 intrc mode ..................................................................... 128 k keeloq evaluation and programming tools.................. 152 m master clear (mclr ) mclr reset, normal operation ............... 129, 131, 132 mclr reset, sleep................................ 129, 131, 132 memory organization data memory .............................................................. 11 program memory ........................................................ 11 mplab integrated development environment software .. 149 multi-master communication ............................................ 103 multi-master mode .............................................................. 85 o opcode field descriptions ............................................. 141 operation ....................................................................... 45 option_reg register ...................................................... 17 intedg bit ................................................................. 17 ps bits .................................................................. 17, 47 psa bit.................................................................. 17, 47 rbpu bit..................................................................... 17 t0cs bit................................................................ 17, 47 t0se bit................................................................ 17, 47 oscillator configuration..................................................... 126 clkout ................................................................... 128 dual speed operation for er and intrc modes .... 128 ec ............................................................. 126, 127, 131 er ..................................................................... 126, 131 er mode ................................................................... 128 hs ..................................................................... 126, 131 intrc ............................................................... 126, 131 lp...................................................................... 126, 131 xt ..................................................................... 126, 131 oscillator, timer1 .......................................................... 49, 51 oscillator, wdt ................................................................. 137 p p.......................................................................................... 68 packaging ......................................................................... 179 paging, program memory ............................................. 11, 24 parallel slave port (psp) read/write enable (pspie bit)................................... 19 pcl register................................................................. 13, 14 pclath register ................................................... 13, 14, 15 pcon register ........................................................... 23, 131 picdem-1 low-cost picmicro demo board ................... 151 picdem-2 low-cost pic16cxx demo board................. 151 picdem-3 low-cost pic16cxxx demo board .............. 151 picstart plus entry level development system.......... 151 pie1 register ..................................................................... 19 adie bit ...................................................................... 19 ccp1ie bit ................................................................. 19 pspie bit.................................................................... 19 rcie bit...................................................................... 19 sspie bit.................................................................... 19 tmr1ie bit ................................................................. 19 tmr2ie bit ................................................................. 19 pie2 register ..................................................................... 21 pinout descriptions pic16c717 ................................................................... 9 pic16c770 ................................................................... 7 pic16c770/771 ............................................................ 7 pic16c771 ................................................................... 7 pir1 register ..................................................................... 20 pir2 register ..................................................................... 22 pmcon1 ............................................................................ 43 pointer, fsr ....................................................................... 25 por. see power-on reset porta ............................................................................... 15 initialization................................................................. 28 porta register......................................................... 27 trisa register........................................................... 27 porta register ......................................................... 13, 124 portb ............................................................................... 15 initialization................................................................. 35 portb register......................................................... 35 pull-up enable (rbpu bit).......................................... 17 rb0/int edge select (intedg bit) ........................... 17 rb0/int pin, external .............................................. 136 rb7:rb4 interrupt on change.................................. 136 rb7:rb4 interrupt on change enable (rbie bit)........................................................... 18, 136 rb7:rb4 interrupt on change flag (rbif bit)...................................................... 18, 35, 136 trisb register........................................................... 35 portb register ......................................................... 13, 124 postscaler, timer2 select (toutps bits)................................................. 53 postscaler, wdt................................................................. 47 assignment (psa bit) ........................................... 17, 47 block diagram ............................................................ 48 rate select (ps bits)............................................ 17, 47 switching between timer0 and wdt......................... 48 power-on reset (por)..................... 125, 129, 130, 131, 132 oscillator start-up timer (ost)........................ 125, 130 power control (pcon) register............................... 131 power-down (pd bit) .................................................. 16 power-on reset circuit, external ............................. 130 power-up timer (pwrt) .................................. 125, 130 time-out (to bit)........................................................ 16 time-out sequence .................................................. 131 time-out sequence on power-up..................... 133, 134 pr2 register ...................................................................... 14 prescaler, capture.............................................................. 56 prescaler, timer0 ............................................................... 47 assignment (psa bit) ........................................... 17, 47 block diagram ............................................................ 48 rate select (ps bits)............................................ 17, 47 switching between timer0 and wdt......................... 48 prescaler, timer1 ............................................................... 50 select (t1ckps bits) ................................................. 49
pic16c717/770/771 ds41120a-page 194 advanced information 1999 microchip technology inc. prescaler, timer2................................................................ 59 select (t2ckps bits).................................................. 53 pro mate ii universal programmer............................. 151 program .............................................................................. 43 program counter pcl register............................................................... 24 pclath register ............................................... 24, 136 reset conditions....................................................... 131 program memory ................................................................ 11 interrupt vector ........................................................... 11 paging ................................................................... 11, 24 program memory map ................................................ 11 reset vector ............................................................... 11 program verification.......................................................... 139 programmable brown-out reset (pbor) ................. 129, 130 programming, device instructions .................................... 141 pwm (ccp module)............................................................ 58 block diagram............................................................. 58 ccpr1h:ccpr1l registers...................................... 58 duty cycle................................................................... 59 output diagram........................................................... 59 period.......................................................................... 58 tmr2 to pr2 match ............................................. 53, 58 tmr2 to pr2 match enable (tmr2ie bit) ................. 19 q q-clock ............................................................................... 59 r r/w ..................................................................................... 68 r/w bit ................................................................................ 78 r/w bit ................................................................................ 79 ram. see data memory rce,receive enable bit, rce ............................................ 70 rcreg ............................................................................... 15 rcsta register.................................................................. 15 read/write bit, r/w ............................................................ 68 reading............................................................................ 45 receive overflow indicator bit, sspov .............................. 69 register file ........................................................................ 11 register file map ................................................................ 12 registers fsr summary ............................................................ 15 indf summary ........................................................... 15 intcon summary ...................................................... 15 pcl summary............................................................. 15 pclath summary ..................................................... 15 portb summary ....................................................... 15 sspstat.................................................................... 68 status summary ..................................................... 15 tmr0 summary .......................................................... 15 trisb summary ......................................................... 15 reset......................................................................... 125, 129 block diagram........................................................... 129 brown-out reset (bor). see brown-out reset (bor) mclr reset. see mclr power-on reset (por). see power-on reset (por) reset conditions for all registers ............................ 132 reset conditions for pcon register........................ 131 reset conditions for program counter ..................... 131 reset conditions for status register .................... 131 restart condition enabled bit, rse .................................... 70 revision history ................................................................ 189 rse..................................................................................... 70 s sae ..................................................................................... 70 sck..................................................................................... 71 scl..................................................................................... 78 sda .................................................................................... 78 sdi...................................................................................... 71 sdo .................................................................................... 71 seeval evaluation and programming system............. 152 serial clock, sck ............................................................... 71 serial clock, scl................................................................ 78 serial data address, sda .................................................. 78 serial data in, sdi .............................................................. 71 serial data out, sdo ......................................................... 71 slave select synchronization ............................................. 74 slave select, ss ................................................................. 71 sleep .............................................................. 125, 129, 138 smp .................................................................................... 68 software simulator (mplab-sim) .................................... 150 spe..................................................................................... 70 special features of the cpu ............................................ 125 special function registers ................................................. 13 pic16c717 ................................................................. 13 pic16c717/770/771 ................................................... 13 pic16c770 ................................................................. 13 pic16c771 ................................................................. 13 speed, operating.................................................................. 1 spi master mode............................................................... 73 serial clock................................................................. 71 serial data in .............................................................. 71 serial data out ........................................................... 71 serial peripheral interface (spi) ................................. 67 slave select................................................................ 71 spi clock .................................................................... 73 spi mode .................................................................... 71 spi clock edge select, cke .............................................. 68 spi data input sample phase select, smp ....................... 68 spi master/slave connection............................................. 72 spi module master/slave connection............................................ 72 slave mode................................................................. 74 slave select synchronization ..................................... 74 slave synch timnig .................................................... 74 ss ....................................................................................... 71 ssp..................................................................................... 67 block diagram (spi mode) ......................................... 71 enable (sspie bit) ..................................................... 19 spi mode .................................................................... 71 sspadd ..................................................................... 78 sspbuf ............................................................... 73, 78 sspcon1 .................................................................. 69 sspcon2 .................................................................. 70 sspsr ................................................................. 73, 78 sspstat ............................................................. 68, 77 tmr2 output for clock shift................................. 53, 54 ssp i 2 c ssp i 2 c operation ..................................................... 77 ssp module spi master mode ........................................................ 73 spi master./slave connection.................................... 72 spi slave mode .......................................................... 74 sspcon1 register .................................................... 77 ssp overflow detect bit, sspov....................................... 78 sspadd register............................................................... 14 sspbuf ....................................................................... 15, 78 sspbuf register ............................................................... 13 sspcon register .............................................................. 13 sspcon1..................................................................... 69, 77 sspcon2........................................................................... 70 sspen................................................................................ 69
1999 microchip technology inc. advanced information ds41120a-page 195 pic16c717/770/771 sspif............................................................................ 20, 79 sspm3:sspm0................................................................... 69 sspov.................................................................... 69, 78, 95 sspstat...................................................................... 68, 77 sspstat register ............................................................. 14 stack ................................................................................... 24 start bit (s).......................................................................... 68 start condition enabled bit, sae ........................................ 70 status register ....................................................... 16, 136 c bit ............................................................................ 16 dc bit.......................................................................... 16 irp bit......................................................................... 16 pd bit.......................................................................... 16 rp1:rp0 bits .............................................................. 16 to bit.......................................................................... 16 z bit............................................................................. 16 status register ................................................................... 16 stop bit (p) .......................................................................... 68 stop condition enable bit ................................................... 70 synchronous serial port ..................................................... 67 synchronous serial port enable bit, sspen ...................... 69 synchronous serial port interrupt ....................................... 20 synchronous serial port mode select bits, sspm<3:0>......................................................................... 69 t t1con ................................................................................ 15 t1con register ........................................................... 15, 49 t1ckps bits ............................................................... 49 t1oscen bit.............................................................. 49 t1sync bit................................................................. 49 tmr1cs bit ................................................................ 49 tmr1on bit................................................................ 49 t2con register ........................................................... 15, 53 t2ckps bits ............................................................... 53 tmr2on bit................................................................ 53 toutps bits .............................................................. 53 timer0 ................................................................................. 47 block diagram............................................................. 47 clock source edge select (t0se bit)................... 17, 47 clock source select (t0cs bit)............................ 17, 47 overflow enable (t0ie bit) ......................................... 18 overflow flag (t0if bit)...................................... 18, 136 overflow interrupt ............................................... 48, 136 timer1 ................................................................................. 49 block diagram............................................................. 50 capacitor selection..................................................... 51 clock source select (tmr1cs bit) ............................ 49 external clock input sync (t1sync bit) .................... 49 module on/off (tmr1on bit)..................................... 49 oscillator ............................................................... 49, 51 oscillator enable (t1oscen bit) ............................... 49 overflow enable (tmr1ie bit).................................... 19 overflow interrupt ................................................. 49, 51 special event trigger (ccp)................................. 51, 57 t1con register ......................................................... 49 tmr1h register ......................................................... 49 tmr1l register.......................................................... 49 timer2 block diagram............................................................. 54 pr2 register......................................................... 53, 58 ssp clock shift..................................................... 53, 54 t2con register ......................................................... 53 tmr2 register............................................................ 53 tmr2 to pr2 match enable (tmr2ie bit) ................. 19 tmr2 to pr2 match interrupt ......................... 53, 54, 58 timing diagrams acknowledge sequence timing ................................. 98 baud rate generator with clock arbitration............... 86 brg reset due to sda collision............................. 105 brown-out reset....................................................... 164 bus collision start condition timing ...................................... 104 bus collision during a restart condition (case 1)... 106 bus collision during a restart condition (case2).... 106 bus collision during a start condition (scl = 0) ..... 105 bus collision during a stop condition...................... 107 bus collision for transmit and acknowledge ........... 103 capture/compare/pwm ........................................... 166 clkout and i/o ...................................................... 162 external clock timing............................................... 162 i 2 c master mode first start bit timing ........................ 87 i 2 c master mode reception timing............................. 97 i 2 c master mode transmission timing ....................... 94 master mode transmit clock arbitration .................. 102 power-up timer ........................................................ 164 repeat start condition ............................................... 89 reset ........................................................................ 164 slave synchronization ................................................ 74 start-up timer........................................................... 164 stop condition receive or transmit......................... 100 time-out sequence on power-up..................... 133, 134 timer0 ...................................................................... 165 timer1 ...................................................................... 165 wake-up from sleep via interrupt .......................... 139 watchdog timer ....................................................... 164 tmr0 .................................................................................. 15 tmr0 register.................................................................... 13 tmr1h ............................................................................... 15 tmr1h register ................................................................. 13 tmr1l ................................................................................ 15 tmr1l register.................................................................. 13 tmr2 .................................................................................. 15 tmr2 register.................................................................... 13 trisa register........................................................... 14, 124 trisb register........................................................... 14, 124 txreg ............................................................................... 15 u update address, ua ........................................................... 68 usart receive enable (rcie bit) ......................................... 19 w w register ........................................................................ 136 wake-up from sleep............................................... 125, 138 interrupts .......................................................... 131, 132 mclr reset ............................................................. 132 timing diagram ........................................................ 139 wdt reset ............................................................... 132 watchdog timer (wdt)............................................ 125, 137 block diagram .......................................................... 137 enable (wdte bit) ................................................... 137 programming considerations ................................... 137 rc oscillator ............................................................ 137 time-out period ........................................................ 137 wdt reset, normal operation................. 129, 131, 132 wdt reset, sleep ......................................... 131, 132 waveform for general call address sequence.................. 83 wcol ................................................. 69, 87, 92, 95, 98, 100 wcol status flag.............................................................. 87 write collision detect bit, wcol........................................ 69 www, on-line support ....................................................... 3
pic16c717/770/771 ds41120a-page 196 advanced information 1999 microchip technology inc. notes:
1999 microchip technology inc. advanced information ds41120a-page197 pic16c717/770/771 systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picmicro, picstart, picmaster and pro mate are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. flex rom, mplab and fuzzy- lab are trademarks and sqtp is a service mark of micro- chip in the u.s.a. all other trademarks mentioned herein are the property of their respective companies. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: ? latest microchip press releases ? technical support section with frequently asked questions ? design tips ?device errata ? job postings ? microchip consultant program member listing ? links to other useful web sites related to microchip products ? conferences for products, development sys- tems, technical information and more ? listing of seminars and events 981103
pic16c717/770/771 ds41120a-page198 advanced information 1999 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41120a pic16c717/770/771
1999 microchip technology inc. advanced information ds41120a-page 199 pic16c717/770/771 pic16c717/770/771 product identification system to order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office. * jw devices are uv erasable and can be programmed to any device configuration. jw devices meet the electrical requirement of each oscillator type (including lc devices). sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 786-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. part no. x /xx xxx pattern: qtp, sqtp, code or special requirements package: jw = windowed cerdip so = soic p=pdip ss = ssop temperature range: -=0 c to +70 c i=-40 c to +85 c device pic16c771 : v dd range 4.0v to 5.5v pic16c771t : v dd range 4.0v to 5.5v (tape/reel) pic16lc771 : v dd range 2.5v to 5.5v pic16lc771t: v dd range 2.5v to 5.5v (tape/reel) examples a) pic16c771/p commercial temp., pdip package, normal v dd limits. -
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or oth er intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. al l other trademarks mentioned herein are the property of their respective companies. ? 1999 microchip technology inc. all rights reserved. ? 1999 microchip technology incorporated. printed in the usa. 11/99 printed on recycled paper. americas corporate office microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-786-7200 fax: 480-786-7277 technical support: 480-786-7627 web address: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 4570 westgrove drive, suite 160 addison, tx 75248 tel: 972-818-7423 fax: 972-818-2924 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia pacific unit 2101, tower 2 metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 beijing microchip technology, beijing unit 915, 6 chaoyangmen bei dajie dong erhuan road, dongcheng district new china hong kong manhattan building beijing 100027 prc tel: 86-10-85282100 fax: 86-10-85282104 india microchip technology inc. india liaison office no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?an road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road ta i p e i , ta i wa n , ro c tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5858 fax: 44-118 921-5835 denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 mnchen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 11/15/99 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.

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